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cyrf69213 programmable radio on chip low power cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-07552 rev. *g revised august 18, 2012 programmable radio on chip low power proc? lp features usb 2.0-usb-if certified (tid # 40000552) single device, two functions ? 8-bit, flash based usb perip heral mcu function and 2.4 ghz radio transceiver function in a single device flash based microcontroller function ? m8c based 8-bit cpu, optimized for human interface devices (hid) applications ? 256 bytes of sram ? 8 kbytes of flash memory with eeprom emulation ? in-system reprogrammable through d+/d? pins ? 16-bit free running timer ? low power wake up timer ? 12-bit programmable interval timer with interrupts ? watchdog timer industry-leading 2.4 ghz radio transceiver function ? operates in the unlicensed wo rldwide industrial, scientific and medical (ism) band (2.4 ghz to 2.483 ghz) ? dsss data rates of up to 250 kbps ? gfsk data rate of 1 mbps ? ?97 dbm receive sensitivity ? programmable output power of up to +4 dbm ? auto transaction sequencer (ats) ? framing crc and auto ack ? received signal strength indication (rssi) ? automatic gain control (agc) component reduction ? integrated 3.3 v regulator ? integrated pull up on d? ? gpios that require no external components ? operates off a single crystal flexible i/o ? 2 ma source current on all gpio pins. configurable 8 ma or 50 ma/pin current sink on designated pins ? each gpio pin supports high impedance inputs, configurable pull up, open-drain output, cmos/ttl inputs and cmos output ? maskable interrupts on all i/o pins usb specification compliance ? conforms to usb specification version 2.0 ? conforms to usb hid specification version 1.1 ? supports one low speed usb device address ? supports one control endpoint and two data end points ? integrated usb transceiver operating voltage from 4.0 v to 5.5 v dc operating temperature from 0 to 70 ? c pb-free 40-pin qfn package advanced development tools based on cypress?s psoc ? tools block diagram microcontroller function radio function rfn rfp rfbias xtal 12mhz v reg v bat0 1-2 uf resv v ss 470nf p0_1,3,4,7 p1_6:7 p2_0:1 470nf gnd . . . . . . . irq/gpio miso/gpio xout/gpio pactl/gpio gnd vbus v dd_micro d+/d- 4.7uf p1.2 / v reg p1.5/mosi p1.4/sck p1.3/nss rst mosi sck nss v bat1 v bat2 v cc1 v cc2 v cc3 v io gnd . . . . . 2 2 2 4 1ohm
cyrf69213 document number: 001-07552 rev. *g page 2 of 85 contents applications ...................................................................... 3 functional description ..................................................... 3 functional overview ........................................................ 3 2.4 ghz radio function .............................................. 3 data transmission modes ........................................... 3 usb microcontroller function ...................................... 3 pinouts .............................................................................. 4 pin configurations ........................................................... 5 proc lp functional overview ........................................ 6 ddr mode ................................................................... 6 sdr mode ................................................................... 7 functional block overview .............................................. 8 2.4 ghz radio ............................................................. 8 frequency synthesizer ................................................ 8 baseband and framer ................................................. 8 packet buffers ............................................................. 9 auto transaction sequencer (ats) ............................ 9 interrupts ..................................................................... 9 clocks ............ .............. .............. .............. ........... ......... 9 gpio interface .......................................................... 10 power on reset/low voltage detect ........................ 10 power management .................................................. 10 timers ....................................................................... 10 usb interface ............................................................ 10 low noise amplifier (lna) and received signal strength indication (rssi) .............................................................. 10 spi interface .................................................................... 11 3-wire spi interface .................................................. 11 4-wire spi interface .................................................. 11 spi communication and transactions ...................... 11 spi i/o voltage references ...................................... 12 spi connects to external devices ............................ 12 cpu architecture ............................................................ 12 cpu registers ................................................................. 13 flags register ........................................................... 13 accumulator register ................................................ 13 index register ........................................................... 14 stack pointer register ............................................... 14 cpu program counter high register ....................... 14 cpu program counter low register ........................ 14 addressing modes ......................................................... 15 source immediate ..................................................... 15 source direct ............................................................. 15 source indexed ......................................................... 15 destination direct ...................................................... 15 destination indexed ................................................... 16 destination direct source immediate ........................ 16 destination indexed source immediate .................... 16 source indirect post increment ................................. 17 destination indirect post increment .......................... 17 instruction set summary ............................................... 18 memory organization ..................................................... 19 flash program memory organization ....................... 19 data memory organization ....................................... 20 flash .......................................................................... 20 srom ........................................................................ 20 srom function descriptions .................................... 21 srom table read description ...................................... 24 clocking .......................................................................... 25 clock architecture description .................................. 26 cpu clock during sleep mode ................................. 32 reset .......... .............. .............. ........... ............ ........... ........ 32 power on reset ............................................................... 34 watchdog timer reset .............................................. 34 sleep mode ...................................................................... 34 sleep sequence ........................................................ 34 wakeup sequence .................................................... 35 low voltage detect control ........................................... 37 por compare state ................................................. 37 eco trim register .................................................... 38 general-purpose i/o ports ............................................. 38 port data registers ................................................... 38 gpio port configuration ........................................... 39 gpio configurations for low power mode: .............. 44 serial peripheral interface (spi) .................................... 45 spi data register ...................................................... 46 spi configure register ............................................. 46 timer registers .............................................................. 48 registers ................................................................... 48 interrupt controller ......................................................... 51 architectural description ........................................... 51 interrupt processing .................................................. 52 interrupt latency ....................................................... 52 interrupt registers ..................................................... 52 usb transceiver ............................................................. 56 usb transceiver configuration ................................. 56 vreg control ............................................................ 56 usb serial interface engine (s ie) ........ .............. ........... 57 usb device ..................................................................... 57 endpoint 0 mode ....................................................... 59 endpoint data buffers ............................................... 60 usb mode tables ........................................................... 62 mode column ............................................................ 62 encoding column ...................................................... 62 setup, in, and out columns ................................. 62 details of mode for differing traffic conditions .......... 63 register summary .......................................................... 66 radio function register descriptions ......................... 69 absolute maximum ratings .......................................... 70 dc characteristics ......................................................... 70 rf characteristics .......................................................... 73 ac test loads and waveforms for digital pins .......... 74 ac electrical characteristics ........................................ 75 ordering information ...................................................... 81 package diagram ............................................................ 82 document history page ................................................. 84 sales, solutions, and legal information ...................... 85 worldwide sales and design support ....................... 85 products .................................................................... 85 psoc solutions ......................................................... 85
cyrf69213 document number: 001-07552 rev. *g page 3 of 85 applications the cyrf69213 proc lp low speed is targeted for the following applications: usb bridge for human interface devices (hid) ? wireless mice ? wireless keyboards ? remote controls ? gaming applications usb bridge for general purpose applications ? consumer electronics ? industrial applications ? white goods ? home automation ? personal health functional description proc lp devices are integrated radio and microcontroller functions in the same package to provide a dual role single-chip solution. communication between the microcontroller and the radio is via the spi interface between both functions. functional overview the cyrf69213 is a complete radio system-on-chip device, providing a complete rf system solution with a single device and a few discrete components. the cyrf69213 is designed to implement low cost wireless syste ms operating in the worldwide 2.4 ghz industrial, scientific, and medical (ism) frequency band (2.400 ghz?2.4835 ghz). 2.4 ghz radio function the radio meets the following world wide regulatory requirements: europe ? etsi en 301 489-1 v1.4.1 ? etsi en 300 328-1 v1.3.1 north america ? fcc cfr 47 part 15 japan ? arib std-t66 data transmission modes the radio supports four different data transmission modes: in gfsk mode, data is transmitted at 1 mbps without any dsss in 8dr mode, 1 byte is encoded in each pn code symbol trans- mitted in ddr mode, 2 bits are encoded in each pn code symbol transmitted in sdr mode, a single bit is encoded in each pn code symbol transmitted both 64-chip and 32-chip data pn codes are supported. the four data transmission modes apply to the data after the start of packet (sop). in particular, the packet length, data and crc are all sent in the same mode. usb microcontroller function the microcontroller function is based on the powerful cyrf69213 microcontroller. it is an 8-bit flash programmable microcontroller with integrated low speed usb interface. the microcontroller has up to 14 gpio pins to support usb, ps/2 and other applications. each gpio port supports high impedance inputs, configurable pull up, open drain output, cmos/ttl inputs and cmos output. up to two pins support programmable drive strength of up to 50 ma. additionally each i/o pin can be used to generate a gpio interrupt to the microcontroller. each gpio po rt has its own gpio interrupt vector with the exception of gpio port 0. the microcontroller features an internal oscillator. with the presence of usb traffic, the internal oscillator can be set to precisely tune to usb timing requirements (24 mhz 1.5%). the proc lp has up to 8 kbytes of flash for user?s firmware code and up to 256 bytes of ram for stack space and user variables. the proc lp includes a watchdog timer, a vectored interrupt controller, a 12-bit programmable interval timer with configurable 1 ms interrupt and a 16-bit free running timer with capture registers.
cyrf69213 document number: 001-07552 rev. *g page 4 of 85 pinouts figure 1. 40-pin qfn pinout rf bias v bat2 xtal p2.1 v cc v bat1 p0.4 v cc p0.1 p0.3 v reg p0.7 p1.6 v bat0 l/d p1.7 pactl / gpio v io v dd_1.8 rst rf n nc p2.0 v cc nc nc resv nc gnd rf p v dd_ micro p1. 3 / ss p1. 4 / sck irq / gpio p1. 5 / mosi miso / gpio xout / gpio p1. 2 / v reg_ micro p1.1/d- p1.0/d+ * e- pad bottom side 21 22 23 24 25 26 27 28 29 30 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 40 39 38 37 36 35 34 33 32 31 1 cyrf69213 wirelessusb lp corner tabs
cyrf69213 document number: 001-07552 rev. *g page 5 of 85 pin configurations pin name function 1 p0.4 individually configured gpio 2 xtal_in 12 mhz crystal. external clock in 3, 7, 16 v cc connected to pin 24 via 0.047 ? f capacitor 4 p0.3 individually configured gpio 5 p0.1 individually configured gpio 6, 9, 39 v bat connected to pin 24 via 0.047 ? fshunt capacitor 8 p2.1 gpio. port 2 bit 1 10 rf bias rf pin voltage reference 11 rf p differential rf input to/from antenna 12 gnd ground 13 rf n differential rf to/from antenna 14, 17, 18, 20, 36 nc 15 p2.0 gpio. port 2 bit 0 19 resv reserved. must connect to gnd 21 p1.0 / d+ gpio 1.0 / low speed usb i/o 22 p1.1 / d? gpio 1.1 / low speed usb i/o 23 v dd_micro 4.0?5.5 for 12 mhz cpu/4.75?5.5 for 24 mhz cpu 24 p1.2 / v reg must be configured as 3.3 v output. it must have a 1?2 ? f output capacitor 25 p1.3 / nss slave select spi pin 26 p1.4 / sck serial clock pin from mcu function to radio function 27 irq interrupt output, configure high/low or gpio 28 p1.5 / mosi master out slave in 29 miso master in slave out, from radio function. can be configured as gpio 30 xout bufferd clk, pactl_n or gpio 31 pactl control for external pa or gpio 32 p1.6 gpio. port 1 bit 6 33 v io i/o interface voltage. connected to pin 24 via 0.047 ? f 34 reset radio reset. connected to v dd via 0.47 ? f capacitor or to microcontr oller gpio pin. must have a reset = high event the very first time power is applied to the radio otherwise the state of the radio function control registers is unknown 35 p1.7 gpio. port 1 bit 7 36 v dd_1.8 regulated logic bypass. connected via 0.47 ? f to gnd 37 l/d connected to gnd 38 p0.7 gpio. port 0 bit 7 40 v reg connected to pin 24 41 e-pad must be connected to gnd 42 corner tabs do not connect corner tabs
cyrf69213 document number: 001-07552 rev. *g page 6 of 85 proc lp functional overview the soc is designed to implement wireless device links operating in the worldwide 2.4 ghz ism frequency band. it is intended for systems compliant with worldwide regulations covered by etsi en 301 489-1 v1.41, etsi en 300 328-1 v1.3.1 (europe), fcc cfr 47 part 15 (usa and industry canada) and telec arib_t66_march, 2003 (japan). the soc contains a 2.4 ghz 1 mbps gfsk radio transceiver, packet data buffering, packet fr amer, dsss baseband controller, received signal strength indication (rssi), and spi interface for data transfer and device configuration. the radio supports 98 discrete 1 mhz channels (regulations may limit the use of some of these channels in certain jurisdictions). in dsss modes the baseband performs dsss spreading/despreading, while in gfsk mode (1 mb/s - gfsk) the baseband performs start of frame (sof), end of frame (eof) detection and crc16 generation and checking. the baseband may also be configured to automatically transmit acknowledge (ack) handshake packets whenever a valid packet is received. when in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, except sdr, enabling the implementation of mixed-rate systems in which different devices use different data rates. this also enables the implementation of dynamic data rate systems, which use high data rate s at shorter distances and/or in a low moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments. the mcu function is an 8-bit flash programmable microcontroller with integrated low speed usb interface. the instruction set has been optimized specifically for usb operations, although it can be used for a variety of other embedded applications. the mcu function has up to eight kbytes of flash for user?s code and up to 256 bytes of ram for stack space and user variables. in addition, the mcu function includes a watchdog timer, a vectored interrupt controller, a 16-bit free-running timer, and 12-bit programmable interrupt timer. the mcu function supports in-system programming by using the d+ and d? pins as the serial programming mode interface. the programming protocol is not usb. ddr mode table 1. ddr mode register value description tx_cfg_adr 0x16 32 chip pn code, ddr, pa = 6 rx_cfg_adr 0x4b agc is enabled. lna and attenuator are disabled. fast turn around is disabled, the device uses high side receive injection and hi-lo is disabled. overwrite to receive buffer is enabled and the rx buffer is configured to receive eight bytes maximum. xact_cfg_adr 0x05 autoack is disabled. forcing end state is disabled. the device is configured to transition to idle mode after a receive or transmit. ack timeout is set to 128 s. framing_cfg_adr 0x00 all sop and framing features are disabled. disable len_en=0 if eop is needed. tx_override_adr 0x04 disable transmit crc-16. rx_override_adr 0x14 the receiver rejects packets with a zero seed. the rx crc-16 checker is disabled and the receiver accepts bad packets that do not matc h the seed in crc_seed registers. basically this helps in communication with the first generation radio that does not have crc capabilities. analog_ctrl_adr 0x01 set all slow. when set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio. data32_thold_adr 0x03 sets the number of allowed corrupted bits to 3. eop_ctrl_adr 0x01 sets the number of consecutive symbols for non correlation to detect end of packet. preamble_adr 0xaaaa05 aaaa are the two preamb le bytes.other bytes can also be written into the preamble register file. the number of preamble bytes to be sent should be >4.
cyrf69213 document number: 001-07552 rev. *g page 7 of 85 sdr mode table 2. sdr mode register value description tx_cfg_adr 0x3e 64 chip pn code, sdr mode, pa = 6. rx_cfg_adr 0x4b agc is enabled. lna and attenuator are disabled. fast turn around is disabled, the device uses high side receive injection and hi-lo is disabled. overwrite to receive buffer is enabled and rx buffer is configured to receive eight bytes maximum. enables rxow to allow new packets to be loaded into the receive buffer. this also enables the valid bit which is used by the first generation radio?s error correction firmware. xact_cfg_adr 0x05 autoack is disabled. forcing end state is disabled. the device is configured to transition to idle mode after receive or transmit. ack timeout is set to 128 s. framing_cfg_adr 0x00 all sop and framing features are disabled. disable len_en=0 if eop is needed. tx_override_adr 0x04 disable transmit crc-16. rx_override_adr 0x14 the receiver rejects packets with a zero seed. the rx crc-16 checker is disabled and the receiver accepts bad packets that do not match the seed in the crc_seed registers. basically this helps in communication with the first generation radio that does not have crc capabilities. analog_ctrl_adr 0x01 set all slow. when set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio, for manual ack consistency data64_thold_adr 0x07 sets the number of allowed corrupted bits to 7 which is close to the recommended 12% value. eop_ctrl_adr 0xa1 sets the number of consecutive symbols for non correlation to detect end of packet. preamble_adr 0xaaaa09 aaaa are the two preamble bytes. any other byte can also be wr itten into the preamble register file. the number of preamble bytes to be sent should be >8.
cyrf69213 document number: 001-07552 rev. *g page 8 of 85 functional block overview all the blocks that make up the proc lp are presented here. 2.4 ghz radio the radio transceiver is a dual conversion low if architecture optimized for power and range/robustness. the radio employs channel-matched filters to achieve high performance in the presence of interference. an integrated power amplifier (pa) provides up to +4 dbm transmit power, with an output power control range of 34 db in 7 steps. the supply current of the device is reduced as the rf output power is reduced. frequency synthesizer before transmission or receptio n may commence, it is necessary for the frequency synthesizer to settle. the settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 ? s. the ?fast channels? (<100 ? s settling time) are every third frequency, starting at 2400 mhz up to and including 2472 mhz (for example, 0,3,6,9?....69 & 72). baseband and framer the baseband and framer bloc ks provide the dsss encoding and decoding, sop generation and reception and crc16 generation and checking, and eop detection and length field. data rates and data transmission modes the soc supports four different data transmission modes: in gfsk mode, data is transmitted at 1 mbps, without any dsss. in 8dr mode, 8 bits are encoded in each data_code_adr derived code symbol transmitted. in ddr mode, 2-bits are encoded in each data_code_adr derived code symbol transmitted. (as in the cywusb6934 ddr mode). in sdr mode, 1 bit is encoded in each data_code_adr derived code symbol transmitted. (as in the cywusb6934 standard modes.) both 64-chip and 32-chip data_code_adr codes are supported. the four data transmission modes apply to the data after the sop. in particular the length, data, and crc16 are all sent in the same mode. in general, lower data rates reduces packet error rate in any given environment. by combining the data_code_adr code lengths and data transmission modes described above, the cyrf69213 ic supports the following data rates: 1000 kbps (gfsk) 250 kbps (32-chip 8dr) 125 kbps (64-chip 8dr) 62.5 kbps (32-chip ddr) 31.25 kbps (64-chip ddr) 15.625 kbps (64-chip sdr) lower data rates typically provide longer range and/or a more robust link. link layer modes the cyrf69213 ic device supports the following data packet framing features: sop ? packets begin with a 2-symbol start of packet (sop) marker. this is required in gfsk and 8dr modes, but is optional in ddr mode and is not supported in sdr mode; if framing is disabled then an sop event is inferred whenever two successive correlations are detected. the sop_code_adr code used for the sop is different from that used for the ?body? of the packet, and if desired may be a different length. sop must be configured to be the same length on both sides of the link. eop ? there are two options for detecting the end of a packet. if sop is enabled, then a packet length field may be enabled. gfsk and 8dr must enable the length field. this is the first 8 bits after the sop symbol, and is transmitted at the payload data rate. if the length field is enabled, an end of packet (eop) condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the crc16 (if enabled?see below). the alternative to using the length field is to infer an eop condition from a configurable number of successive non correlations; this option is not available in gfsk mode and is only recommended when using sdr mode. crc16 ? the device may be configured to append a 16-bit crc16 to each packet. the crc16 uses the usb crc polynomial with the added programmability of the seed. if enabled, the receiver verifies the calculated crc16 for the payload data against the received value in the crc16 field. the starting value for the crc16 calculation is configurable, and the crc16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data crc16 is checked against both the configured and zero crc16 seeds. crc16 detects the following errors: any one bit in error any two bits in error (irrespective of how far apart, which column, and so on) any odd number of bits in error (irrespective of the location) an error burst as wide as the checksum itself figure 2 on page 9 shows an example packet with sop, crc16 and lengths fields enabled. table 3. internal pa output power step table pa setting typical output power (dbm) 7+4 60 5?5 4?10 3?15 2?20 1?25 0?30
cyrf69213 document number: 001-07552 rev. *g page 9 of 85 figure 2. example default packet format packet buffers packet data and configuration registers are accessed through the spi interface. all configuration registers are directly addressed through the address field in the spi packet. configuration registers are provided to allow configuration of dsss pn codes, data rate, o perating mode, interrupt masks, interrupt status, and others. packet buffers all data transmission and reception uses the 16-byte packet buffers?one for transmission and one for reception. the transmit buffer allows a complete packet of up to 16 bytes of payload data to be loaded in one burst spi transaction.this is then transmitted with no further mcu intervention. similarly, the receive buffer allows an entire packet of payload data up to 16 bytes to be received with no firmware intervention required until packet reception is complete. the cyrf69213 ic supports packet length of up to 40 bytes; interrupts are provided to allow an mcu to use the transmit and receive buffers as fifos. when transmitting a packet longer than 16 bytes, the mcu can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. similarly, when receiving packets longer than 16 bytes, the mcu function must fetch received data from the fifo periodically during packet reception to prevent it from overflowing. auto transaction sequencer (ats) the cyrf69213 ic provides automated support for transmission and reception of acknowledged data packets. when transmitting a data packet, the device automatically starts the crystal and synthesizer, enters transmit mode, transmits the packet in the transmit buffer, and then automatically switches to receive mode and waits for a handshake packet ? and then automatically reverts to sleep mode or idle mode when either an ack packet is received, or a timeout period expires. similarly, when receiving in transaction mode, the device waits in receive mode for a valid packet to be received, then automatically transitions to tr ansmit mode, transmits an ack packet, and then switches back to receive mode to await the next packet. the contents of the packet buffers are not affected by the transmission or reception of ack packets. in each case, the entire packet transaction takes place without any need for mcu firmware action; to transmit data the mcu simply needs to load the data packet to be transmitted, set the length, and set the tx go bit. similarly, when receiving packets in transaction mode, firmware simply needs to retrieve the fully received packet in response to an interrupt request indicating reception of a packet. interrupts the radio function provides an interrupt (irq) output, which is configurable to indicate the occurrence of various different events. the irq pin may be programmed to be either active high or active low, and be either a cmos or open drain output. the irq pin can be multiplexed on the spi if routed to an external pin. the radio function features three sets of interrupts: transmit, receive, and system interrupts. these interrupts all share a single pin (irq), but can be independently enabled/disabled. in transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. however, the contents of the enable registers are preserved when switching between transmit and receive modes. if more than one radio interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the irq pin to assert. even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. it is therefore possible to use the devices without making use of the irq pin by polling the status register(s) to wait for an event, rather than using the irq pin. the microcontroller function supports 23 maskable interrupts in the vectored interrupt controller . interrupt sources include a usb bus reset, lvr/por, a programmable interval timer, a 1.024-ms output from the free running timer, three usb endpoints, two capture timers, five gpio ports, three gpio pins, two spi, a 16-bit free running timer wrap, an internal wakeup timer, and a bus active interrupt. the wakeup timer causes periodic interrupts when enabled. the usb endpoints interrupt after a usb transaction complete is on the bus. the capture timers interrupt whenever a new timer value is saved due to a selected gpio edge event. a total of eight gpio interrupts support both ttl or cmos thresholds. for additional flexibility, on the edge sensitive gpio pins, the interrupt polarity is programmable to be either rising or falling. clocks the radio function has a 12 mhz crystal (30-ppm or better) directly connected between xtal and gnd without the need for external capacitors. a digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 mhz. this output may be used to clock an external microcontroller (mcu) or asic. this output is enabled by default, but may be disabled. p sop 1 sop 2 length crc 16 payload data preamble n x 16us 1st framing symbol* 2nd framing symbol* packet length 1 byte period *note:32 or 64us
cyrf69213 document number: 001-07552 rev. *g page 10 of 85 following are the requirements for the crystal to be directly connected to xtal pin and gnd: nominal frequency: 12 mhz operating mode: fundamental mode resonance mode: parallel resonant frequency stability: 30 ppm series resistance: < 60 ohms load capacitance: 10 pf drive level:100 ? w the mcu function features an internal oscillator. with the presence of usb traffic, the internal oscillator can be set to precisely tune to usb timing requirements (24 mhz 1.5%). the clock generator provides the 12 mhz and 24 mhz clocks that remain internal to the microcontroller. gpio interface the mcu function features up to 20 general purpose i/o (gpio) pins to support usb, ps/2, and other applications. the i/o pins are grouped into five ports (port 0 to 4). the pins on port 0 and port 1 may each be configured individually while the pins on ports 2, 3, and 4 may only be configured as a group. each gpio port supports high impedance inputs, configurable pull up, open drain output, cmos/ttl inputs, and cmos output with up to five pins that support programmable drive strength of up to 50 ma sink current. gpio port 1 features four pins that interface at a voltage level of 3.3 volts. additionally, each i/o pin can be used to generate a gpio interrupt to the microcontroller. each gpio port has its own gpio interrupt vector with the exception of gpio port 0. gpio port 0 has three dedicated pins that have independent interrupt vectors (p0.3?p0.4). power on reset/low voltage detect the power on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at flash address 0x0000. when power falls below a programmable trip voltage, it generates reset or may be configured to generate interrupt. there is a low voltage detect circuit that detects when v cc drops below a programmable trip voltage. it may be configurable to generate an lvd interrupt to inform the processor about the low voltage event. por and lvd share the same interrupt. there is not a separate interrupt for each. the watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. power management the device draws its power supply from the usb v bus line. the v bus supplies power to the mcu function, which has an internal 3.3 v regulator. this 3.3 v is supplied to the radio function via p1.2/v reg after proper filtering as shown in figure 3 . figure 3. power management from internal regulator timers the free-running 16-bit timer provides two interrupt sources: the programmable interval timer with 1 ? s resolution and the 1.024 ms outputs. the timer can be used to measure the duration of an event under firmware control by reading the timer at the start and at the end of an event, then calculating the difference between the two values. usb interface the mcu function includes an integrated usb serial interface engine (sie) that allows the chip to easily interface to a usb host. the hardware supports one usb device address with three endpoints. low noise amplifier (lna) and received signal strength indication (rssi) the gain of the receiver may be controlled directly by clearing the agc en bit and writing to the low noise amplifier (lna) bit of the rx_cfg_adr register. when the lna bit is cleared, the receiver gain is reduced by approximately 20 db, allowing accurate reception of very strong received signals (for example when operating a receiver very close to the transmitter). an additional 20 db of receiver attenuation can be added by setting the attenuation (att) bit; this allows data reception to be limited to devices at very short ranges. disabling agc and enabling lna is recommended unless receiving from a device using external pa. the rssi register returns the relative signal strength of the on-channel signal power. when receiving, the device may be configured to automatically measure and store the relative strength of the signal being received as a 5-bit value. when enabled, an rssi reading is taken and may be read through the spi interface. an rssi proc lp v reg v bat0 v bat1 v bat2 v cc1 v cc2 v cc3 l/d v io 0.047f 0.047f 0.047f 0.047f 0.047f 0.047f 0.047f 0.047f v dd_micro v dd 0.1f p1.2 / v reg 1 ohm
cyrf69213 document number: 001-07552 rev. *g page 11 of 85 reading is taken automatically when the start of a packet is detected. in addition, a new rssi reading is taken every time the previous reading is read from the rssi register, allowing the background rf energy level on any given channel to be easily measured when rssi is read when no signal is being received. a new reading can occur as fast as once every 12 ? s. receive spurious response the transmitter may exhibit spurs around 50mhz offset at levels approximately 50db to 60db below the carrier power. receivers operating at the transmit spur frequency may receive the spur if the spur level power is greater than the receive sensitivity level. the workaround for this is to program an additional byte in the packet header which contains the transmitter channel number. after the packet is received, the channel number can be checked. if the channel number does not match the receive channel then the pa cket is rejected. spi interface the spi interface between the mcu function and the radio function is a 3-wire spi interface. the three pins are mosi (master out slave in), sck (ser ial clock), ss (slave select). there is an alternate 4-wire miso interface that requires the connection of two external pins. the spi interface is controlled by configuring the spi configure register (sicr address: 0x3d). 3-wire spi interface the radio function receives a clock from the mcu function on the sck pin. the mosi pin is multiplexed with the miso pin. bidirectional data transfer takes place between the mcu function and the radio function through this multiplexed mosi pin. when using this mode the user firmware should ensure that the mosi pin on the mcu function is in a high impedance state, except when the mcu is actively transmitting data. firmware must also control the direction of data flow and switch directions between mcu function and radio function by setting the swap bit [bit 7] of the spi configure register. the ss pin is asserted prior to initiating a data transfer between the mcu function and the radio function. the irq function may be optionally multiplexed with the mosi pin; when this option is enabled the irq function is not available while the ss pin is low. when using this configuration, user firmware should ensure that the mosi function on mcu function is in a high impedance state whenever ss is high. figure 4. 3-wire spi mode 4-wire spi interface the 4-wire spi communications interface consists of mosi, miso, sck, and ss. the device receives sck from the mcu function on the sck pin. data from the mcu function is shifted in on the mosi pin. data to the mcu function is shifted out on the miso pin. the active low ss pin must be asserted for the two functions to communicate. the irq function may be optionally multiplexed with the mosi pin; when this option is enabled the irq function is not available while the ss pin is low. when using this configuration, user firmware should ensure that the mosi function on mcu function is in a high impedance state whenever ss is high. figure 5. 4-wire spi mode spi communication and transactions the spi transactions can be single byte or multi-byte. the mcu function initiates a data transfer through a command/address byte. the following bytes are data bytes. the spi transaction format is shown in figure 6 . the dir bit specifies the direction of data transfer. 0 = master reads from slave. 1 = master writes to slave. the inc bit helps to read or write consecutive bytes from contiguous memory locations in a single burst mode operation. if slave select is asserted and inc = 1, then the master mcu function reads a byte from the radio, the address is incremented by a byte location, and then the byte at that location is read, and so on. if slave select is asserted and inc = 0, then the mcu function reads/writes the bytes in the same register in burst mode, but if it is a register file then it reads/writes the bytes in that register file. the spi interface between the radio function and the mcu is not dependent on the internal 12 mhz oscillator of the radio. therefore, radio function registers can be read from or written into while the radio is in sleep mode. mcu function p1.5/mosi p1.4/sck p1.3/nss mosi sck nss radio function mosi sck nss mosi/miso multiplexed on one mosi pin mcu function p1.5/mosi p1.4/sck p1.3/nss p1.6/miso mosi sck nss radio function miso mosi sck nss this connection is external to the proc lp chip
cyrf69213 document number: 001-07552 rev. *g page 12 of 85 spi i/o voltage references the spi interfaces between mcu function and the radio and the irq and rst have a separate voltage reference v io , enabling the radio function to directly interface with the mcu function, which operates at higher supply voltage. the internal spio pins between the mcu function and radio function should be connected with a regulated voltage of 3.3 v (by setting [bit4] of registers p13cr, p14cr, p15cr, and p16cr of the mcu function) and the internal 3.3 v regulator of the mcu function should be turned on. spi connects to external devices the three spi wires, mosi, sck, and ss are also drawn out of the package as external pins to allow the user to interface their own external devices (such as optical sensors and others) through spi. the radio function also has its own spi wires miso and irq, which can be used to send data back to the mcu function or send an interrupt request to the mcu function. they can also be configured as gpio pins. cpu architecture this family of microcontroller is based on a high performance, 8-bit, harvard-architecture mi croprocessor. five registers control the primary operation of the cpu core. these registers are affected by various instructions, but are not directly accessible through the register space by the user. the 16-bit program counter register (cpu_pc) allows for direct addressing of the full eight kbytes of program memory space. the accumulator register (cpu_a) is the general purpose register that holds the results of instructions that specify any of the source addressing modes. the index register (cpu_x) holds an offset value that is used in the indexed addressing modes. typically, this is used to address a block of data within the data memory space. the stack pointer register (cpu_sp) holds the address of the current top-of-stack in the data me mory space. it is affected by the push, pop, lcall, call, reti, and ret instructions, which manage the software stack. it can also be affected by the swap and add instructions. the flag register (cpu_f) has three status bits: zero flag bit [1]; carry flag bit [2]; supervisory state bit [3]. the global interrupt enable bit [0] is used to globally enable or disable interrupts. the user cannot manipulate the supervisory state status bit [3]. the flags are affected by arithmetic, logic, and shift operations. the manner in which each flag is changed is dependent upon the instruction being executed (for example, and, or, xor). see table 21 on page 18 . figure 6. spi transaction format byte 1 byte 1+n bit# 7 6 [5:0] [7:0] bit name dir inc address data table 4. cpu registers and register names register register name flags cpu_f program counter cpu_pc accumulator cpu_a stack pointer cpu_sp index cpu_x
cyrf69213 document number: 001-07552 rev. *g page 13 of 85 cpu registers flags register the flags register can only be set or reset with logical instruction. accumulator register table 5. cpu flags register (cpu_f) [r/w] bit # 7 6 5 4 3 2 1 0 field reserved xio super carry zero global ie read/write ???r/wrrwrwrw default 00000010 bits 7:5 reserved bit 4 xio set by the user to select between the register banks 0 = bank 0 1 = bank 1 bit 3 super indicates whether the cpu is executing us er code or supervisor code. (this code cannot be accessed directly by the user.) 0 = user code 1 = supervisor code bit 2 carry set by cpu to indicate whether there has been a ca rry in the previous logical/arithmetic operation 0 = no carry 1 = carry bit 1 zero set by cpu to indicate whether there has been a zero result in the previous logical/arithmetic operation 0 = not equal to zero 1 = equal to zero bit 0 global ie determines whether all interrupts are enabled or disabled 0 = disabled 1 = enabled note cpu_f register is only readable with explicit register address 0xf7. the or f, expr and and f, expr instructions must be used to set and clear the cpu_f bits table 6. cpu accumulator register (cpu_a) bit # 7 6 5 4 3 2 1 0 field cpu accumulator [7:0] read/write ???????? default 00000000 bits 7:0 cpu accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mod e
cyrf69213 document number: 001-07552 rev. *g page 14 of 85 index register stack pointer register cpu program counter high register cpu program counter low register table 7. cpu x register (cpu_x) bit # 7 6 5 4 3 2 1 0 field x [7:0] read/write ???????? default 00000000 bits 7:0 x [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode table 8. cpu stack pointer register (cpu_sp) bit # 7 6 5 4 3 2 1 0 field stack pointer [7:0] read/write ???????? default 00000000 bits 7:0 stack pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack table 9. cpu program coun ter high register (cpu_pch) bit # 7 6 5 4 3 2 1 0 field program counter [15:8] read/write ???????? default 00000000 bits 7:0 program counter [15:8] 8-bit data value holds the higher byte of the program counter table 10. cpu program coun ter low register (cpu_pcl) bit # 7 6 5 4 3 2 1 0 field program counter [7:0] read/write ???????? default 00000000 bits 7:0 program counter [7:0] 8-bit data value holds the lower byte of the program counter
cyrf69213 document number: 001-07552 rev. *g page 15 of 85 addressing modes examples of the different addressing modes are discussed in this section and example code is given. source immediate the result of an instruction using this addressing mode is placed in the a register, the f register, the sp register, or the x register, which is specified as part of the instruction opcode. operand 1 is an immediate value that serves as a source for the instruction. arithmetic instructions require two sources. instructions using this addressing mode are two bytes in length. examples source direct the result of an instruction using this addressing mode is placed in either the a register or the x register, which is specified as part of the instruction opcode. operand 1 is an address that points to a location in either the ram memory space or the register space that is the source for the instruction. arithmetic instructions require two sources; the second source is the a register or x register specified in the opcode. instructions using this addressing mode are two bytes in length. examples source indexed the result of an instruction using this addressing mode is placed in either the a register or the x register, which is specified as part of the instruction opcode. operand 1 is added to the x register forming an address that points to a location in either the ram memory space or the register space that is the source for the instruction. arithmetic instructions require two sources; the second source is the a register or x register specified in the opcode. instructions using this addressing mode are two bytes in length. examples destination direct the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is an address that points to the location of the result. the source for the instruction is either the a register or the x register, which is specified as part of the instruction opcode. arithmetic instructions require two sources; the second source is the location specified by operand 1. instructions using this addressing mode are two bytes in length. examples table 11. source immediate opcode operand 1 instruction immediate value add a, 7 ;in this case, the immediate value ;of 7 is added with the accumulator, ;and the result is placed in the ;accumulator. mov x, 8 ;in this case, the immediate value ;of 8 is moved to the x register. and f, 9 ;in this case, the immediate value ;of 9 is logically anded with the f ;register and the result is placed ;in the f register. table 12. source direct opcode operand 1 instruction source address add a, [7] ;in this case, the value in ;the ram memory location at ;address 7 is added with the ;accumulator, and the result ;is placed in the accumulator. mov x, reg[8] ;in this case, the value in ;the register space at address ;8 is moved to the x register. table 13. source indexed opcode operand 1 instruction source index add a, [x+7] ;in this case, the value in ;the memory location at ;address x + 7 is added with ;the accumulator, and the ;result is placed in the ;accumulator. mov x, reg[x+8] ;in this case, the value in ;the register space at ;address x + 8 is moved to ;the x register. table 14. destination direct opcode operand 1 instruction destination address add [7], a ;in this case, the value in ;the memory location at ;address 7 is added with the ;accumulator, and the result ;is placed in the memory ;location at address 7. the ;accumulator is unchanged. mov reg[8], a ;in this case, the accumula- ;tor is moved to the regis- ;ter space location at ;address 8. the accumulator ;is unchanged.
cyrf69213 document number: 001-07552 rev. *g page 16 of 85 destination indexed the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x register forming the address that points to the location of the result. the source for the instruction is the a register. arithmetic instructions require two sources; the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are two bytes in length. example destination direct source immediate the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is the address of the result. the source for the instruction is operand 2, which is an immediate value. arithmetic instructions require two sources; the second source is the location specified by operand 1. instructions using this addressing mode are three bytes in length. examples destination indexed source immediate the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x register to form the address of the result. the source for the instruction is operand 2, which is an immediate value. arithmetic instructions require two sources; the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are three bytes in length. examples destination direct source direct the result of an instruction using this addressing mode is placed within the ram memory. operand 1 is the address of the result. operand 2 is an address that points to a location in the ram memory that is the source for the instruction. this addressing mode is only valid on the mov in struction. the instruction using this addressing mode is three bytes in length. example table 15. destination indexed opcode operand 1 instruction destination index add [x+7], a ;in this case, the value in the ;memory location at address x+7 ;is added with the accumulator, ;and the result is placed in ;the memory location at address ;x+7. the accumulator is ;unchanged. table 16. destination direct immediate opcode operand 1 operand 2 instruction destination address immediate value add [7], 5 ;in this case, value in the mem- ;ory location at address 7 is ;added to the immediate value of ;5, and the result is placed in ;the memory location at address 7. mov reg[8], 6 ;in this case, the immediate ;value of 6 is moved into the ;register space location at ;address 8. table 17. destination indexed immediate opcode operand 1 operand 2 instruction destination index immediate value add [x+7], 5 ;in this case, the value in ;the memory location at ;address x+7 is added with ;the immediate value of 5, ;and the result is placed ;in the memory location at ;address x+7. mov reg[x+8], 6 ;in this case, the immedi- ;ate value of 6 is moved ;into the location in the ;register space at ;address x+8. table 18. destination direct source direct opcode operand 1 operand 2 instruction destination address source address mov [7], [8] ;in this case, the value in the ;memory location at address 8 is ;moved to the memory location at ;address 7.
cyrf69213 document number: 001-07552 rev. *g page 17 of 85 source indirect post increment the result of an instruction using this addressing mode is placed in the accumulator. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. the indirect address is incremented as part of the instruction execution. this addressing mode is only valid on the mvi instruction. the instruction using this addressing mode is two bytes in length. refer to the psoc designer: assembly language user guide for further details on mvi instruction. example destination indirect post increment the result of an instruction using this addressing mode is placed within the memory space. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. the indirect address is incremented as part of the instruction execution. the source for the instruction is the accumulator. this addressing mode is only valid on the mvi instruction. the instruction using this addressing mode is two bytes in length. example table 19. source indirect post increment opcode operand 1 instruction source address address mvi a, [8] ;in this case, the value in the ;memory location at address 8 is ;an indirect address. the memory ;location pointed to by the indi- ;rect address is moved into the ;accumulator. the indirect ;address is then incremented. table 20. destination indirect post increment opcode operand 1 instruction destination address address mvi [8], a ;in this case, the value in ;the memory location at ;address 8 is an indirect ;address. the accumulator is ;moved into the memory loca- ;tion pointed to by the indi- ;rect address. the indirect ;address is then incremented.
cyrf69213 document number: 001-07552 rev. *g page 18 of 85 instruction set summary the instruction set is summarized in ta b l e 2 1 numerically and serves as a quick reference. if more information is needed, the instruction set summary tables are described in detail in the psoc designer assembly language user guide (available on www.cypress.com ). table 21. instruction set summary sorted numerically by opcode order [1, 2] opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags 00 15 1 ssc 2d 8 2 or [x+expr], a z 5a 5 2 mov [expr], x 01 4 2 add a, expr c, z 2e 9 3 or [expr], expr z 5b 4 1 mov a, x z 02 6 2 add a, [expr] c, z 2f 10 3 or [x+expr], expr z 5c 4 1 mov x, a 03 7 2 add a, [x+expr] c, z 30 9 1 halt 5d 6 2 mov a, reg[expr] z 04 7 2 add [expr], a c, z 31 4 2 xor a, expr z 5e 7 2 mov a, reg[x+expr] z 05 8 2 add [x+expr], a c, z 32 6 2 xor a, [expr] z 5f 10 3 mov [expr], [expr] 06 9 3 add [expr], expr c, z 33 7 2 xor a, [x+expr] z 60 5 2 mov reg[expr], a 07 10 3 add [x+expr], expr c, z 34 7 2 xor [expr], a z 61 6 2 mov reg[x+expr], a 08 4 1 push a 35 8 2 xor [x+expr], a z 62 8 3 mov reg[expr], expr 09 4 2 adc a, expr c, z 36 9 3 xor [expr], expr z 63 9 3 mov reg[x+expr], expr 0a 6 2 adc a, [expr] c, z 37 10 3 xor [x+expr], expr z 64 4 1 asl a c, z 0b 7 2 adc a, [x+expr] c, z 38 5 2 add sp, expr 65 7 2 asl [expr] c, z 0c 7 2 adc [expr], a c, z 39 5 2 cmp a, expr if (a=b) z=1 if (a cyrf69213 document number: 001-07552 rev. *g page 19 of 85 memory organization flash program memory organization table 22. program memory space with interrupt vector table after reset address 16-bit pc 0x0000 program execution begins here after a reset 0x0004 por/lvd 0x0008 int0 0x000c spi transmitter empty 0x0010 spi receiver full 0x0014 gpio port 0 0x0018 gpio port 1 0x001c int1 0x0020 ep0 0x0024 ep1 0x0028 ep2 0x002c usb reset 0x0030 usb active 0x0034 1 ms interval timer 0x0038 programmable interval timer 0x003c reserved 0x0040 reserved 0x0044 16-bit free running timer wrap 0x0048 int2 0x004c reserved 0x0050 gpio port 2 0x0054 reserved 0x0058 reserved 0x005c reserved 0x0060 reserved 0x0064 sleep timer 0x0068 program memory begins here (if below interrupts not used, program memory can start lower) 0x1fff 8 kb ends here
cyrf69213 document number: 001-07552 rev. *g page 20 of 85 data memory organization the mcu function has 256 bytes of data ram. flash this section describes the flash block of the cyrf69213. much of the user-visible flash functionality, including programming and security, are implemented in the m8c supervisory read only memory (srom). cyrf69213 flash has an endurance of 1000 cycles and 10 year data retention. flash programming and security all flash programming is performed by code in the srom. the registers that control the flash programming are only visible to the m8c cpu when it is executing out of srom. this makes it impossible to read, write, or erase the flash by bypassing the security mechanisms impl emented in the srom. customer firmware can only program the flash via srom calls. the data or code images can be sourced by way of any interface with the appropriate support firmware. this type of programming requires a ?boot-loader? ? a piece of firmware resident on the flash. for safety reasons this boot-loader should not be overwritten during firmware rewrites. the flash provides four auxiliary rows that are used to hold flash block protection flags, boot time calibration values, configuration tables, and any device values. the routines for accessing these auxiliary rows are documented in the srom section. the auxiliary rows are not affected by the device erase function. in-system programming most designs that include an cyrf69213 part have a usb connector attached to the usb d+/d? pins on the device. these designs require the ability to program or reprogram a part through these two pins alone. cyrf69213 device enables this type of in-system programming by using the d+ and d? pins as the serial programming mode interface. this allows an external controller to cause the cyrf69213 part to enter serial programming mode and then to use the test queue to issue flash access functions in the srom. the programming protocol is not usb. srom the srom holds code that is used to boot the part, calibrate circuitry, and perform flash operations. ( table 24 lists the srom functions.) the functions of the srom may be accessed in normal user code or operating from flash. the srom exists in a separate memory space from user code. the srom functions are accessed by executing the supervisory system call instruction (ssc), which has an opcode of 00h. prior to executing the ssc, the m8c?s accumulator needs to be loaded with the desired srom function code from table 24 . undefined functions causes a halt if called from user code. the srom functions are executing code with calls; therefore, the functions require stack space. with the exception of reset, all of the srom functions have a parameter block in sram that must be configured before executing the ssc. table 25 lists all possible parameter block variables. the meaning of each parameter, with regards to a specific srom function, is described later in this section. two important variables that are used for all functions are key1 and key2. these variables are used to help discriminate between valid sscs and inadvert ent sscs. key1 must always have a value of 3ah, while key2 must have the same value as the stack pointer when the srom function begins execution. this would be the stack pointer value when the ssc opcode is table 23. data memory organization after reset address 8-bit psp 0x00 stack begins here and grows upward. top of ram memory 0xff table 24. srom function codes function code function name stack space 00h swbootreset 0 01h readblock 7 02h writeblock 10 03h eraseblock 9 05h eraseall 11 06h tableread 3 07h checksum 3
cyrf69213 document number: 001-07552 rev. *g page 21 of 85 executed, plus three. if either of the keys do not match the expected values, the m8c halts (with the exception of the swbootreset function). the following code puts the correct value in key1 and key2. the code st arts with a halt, to force the program to jump directly into the setup code and not run into it. halt sscop: mov [key1], 3ah mov x, sp mov a, x add a, 3 mov [key2], a the srom also features return codes and lockouts. return codes return codes aid in the determination of success or failure of a particular function. the return code is stored in key1?s position in the parameter block. the checksum and tableread functions do not have return codes because key1?s position in the parameter block is used to return other data. read, write, and erase operations may fail if the target block is read or write protected. block protection levels are set during device programming. the eraseall function overwrites data in addition to leaving the entire user flash in the erase state. the eraseall function loops through the number of flash macros in the product, executing the following sequence: erase, bulk program all zeros, erase. after all the user space in all the flash macros are erased, a second loop erases and then programs each protection block with zeros. srom function descriptions all srom functions are described in the following sections. swbootreset function the srom function, swbootreset, is the function that is responsible for transitioning the device from a reset state to running user code. the swbootreset function is executed whenever the srom is entered with an m8c accumulator value of 00h; the sram parameter block is not used as an input to the function. this happens, by design, after a hardware reset, because the m8c's accumulator is reset to 00h or when user code executes the ssc instruction with an accumulator value of 00h. the swbootreset function does not execute when the ssc instruction is executed with a bad key value and a nonzero function code. a cyrf69213 device executes the halt instruction if a bad value is given for either key1 or key2. the swbootreset function verifies the integrity of the calibration data by way of a 16-bit checksum, before releasing the m8c to run user code. readblock function the readblock function is used to read 64 contiguous bytes from flash ? a block. the first thing this function does is to check the protection bits and determine if the desired blockid is readable. if read protection is turned on, the readblock function exits, setting the accumulator and key2 back to 00h. key1 has a value of 01h, indicating a read failure. if read protection is not enabled, the function reads 64 bytes from the flash using a romx instruction and store the results in sram using an mvi instruction. the first of the 64 bytes is stored in sram at the address indicated by the value of the pointer parameter. when the readblock completes successfully, the a ccumulator, key1, and key2 all have a value of 00h. writeblock function the writeblock function is used to store data in the flash. data is moved 64 bytes at a time from sram to flash using this function. the first thing the writeblock function does is to check the protection bits and determine if the desired blockid is writable. if write protection is turned on, the writeblock function exits, setting the a ccumulator and key2 ba ck to 00h. key1 has a value of 01h, indicating a write failure. the configuration of the writeblock function is straightforward. the blockid of the flash block, where the data is stored, must be determined and stored at sram address fah. table 25. srom function parameters variable name sram address key1/counter/return code 0,f8h key2/tmp 0,f9h blockid 0,fah pointer 0,fbh clock 0,fch mode 0,fdh delay 0,feh pcl 0,ffh table 26. srom return codes return code description 00h success 01h function not allowed due to level of protection on block 02h software reset with out hardware reset 03h fatal error, srom halted table 27. readblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer va lue, when ssc is executed blockid 0,fah flash block number pointer 0,fbh first of 64 addresses in sram where returned data should be stored
cyrf69213 document number: 001-07552 rev. *g page 22 of 85 the sram address of the first of the 64 bytes to be stored in flash must be indicated using the pointer variable in the parameter block (sram address fbh). finally, the clock and delay values must be set correctly. the clock value determines the length of the write pulse that is used to store the data in the flash. the clock and delay values are dependent on the cpu speed. refer to ?clocking? section for additional information. eraseblock function the eraseblock function is used to erase a block of 64 contiguous bytes in flash. the first thing the eraseblock function does is to check the protection bits and determine if the desired blockid is writable. if write protection is turned on, the eraseblock function exits, se tting the accumulator and key2 back to 00h. key1 has a value of 01h, indicating a write failure. the eraseblock function is only useful as the first step in programming. erasing a block does not cause data in a block to be one hundred percent unreadable. if the objective is to obliterate data in a block, the best method is to perform an eraseblock followed by a writeblock of all zeros. to set up the parameter block for the eraseblock function, correct key values must be stored in key1 and key2. the block number to be erased must be stored in the blockid variable and the clock and delay values must be set based on the current cpu speed. protectblock function the cyrf69213 device offers flash protection on a block-by-block basis. table 30 lists the protection modes available. in the table, er and ew are used to indicate the ability to perform external reads and writes. for internal writes, iw is used. internal reading is always permitted by way of the romx instruction. the ability to read by way of the srom readblock function is indicated by sr. the protection level is stored in two bits according to ta b l e 3 0 . these bits are bit packed into the 64 bytes of the protection block. therefore, each protection block byte stores the protection level fo r four flash blo cks. the bits are packed into a byte, with the lowest numbered block?s protection level stored in the lowest numbered bits. the first address of the protection block contains the protection level for blocks 0 through 3; t he second address is for blocks 4 through 7. the 64th byte stores the protection level for blocks 252 through 255. the level of protection is only decreased by an eraseall, which places zeros in all locations of the protection block. to set the level of protection, the protectblock function is used. this function takes data from sram, starting at address 80h, and ors it with the current values in the protection block. the result of the or operation is then stored in the protection block. the eraseblock function does not change the protection level for a block. because the sram location for the protection data is fixed and there is only one protection block per flash macro, the protectblock function expects very few variables in the parameter block to be set prior to calling the function. the parameter block values that must be set, besides the keys, are the clock and delay values. table 28. writeblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed blockid 0,fah 8 kb flash block number (00h?7fh) 4 kb flash block number (00h?3fh) 3 kb flash block number (00h?2fh) pointer 0,fbh first of 64 addresses in sram, where the data to be stored in flash is located prior to calling writeblock clock 0,fch clock divider used to set the write pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 29. eraseblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed blockid 0,fah flash block number (00h?7fh) clock 0,fch clock divider used to set the erase pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 30. protection modes mode settings description marketing 00b sr er ew iw unprotected unprotected 01b sr er ew iw read protect factory upgrade 10b sr er ew iw disable external write field upgrade 11b sr er ew iw disable internal write full protection 7 6 5 4 3 2 1 0 block n+3 block n+ 2 block n+1 block n table 31. protectblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed clock 0,fch clock divider used to set the write pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h
cyrf69213 document number: 001-07552 rev. *g page 23 of 85 eraseall function the eraseall function performs a series of steps that destroy the user data in the flash macros and resets the protection block in each flash macro to all zeros (the unprotected state). the eraseall function does not affe ct the three hidden blocks above the protection block in each flash macro. the first of these four hidden blocks is used to store t he protection table for its eight kbytes of user data. the eraseall function begins by erasing the user space of the flash macro with the highest address range. a bulk program of all zeros is then performed on the same flash macro, to destroy all traces of the previous contents. the bulk program is followed by a second erase that leaves the flash macro in a state ready for writing. the erase, pr ogram, erase sequence is then performed on the next lowest flash macro in the address space if it exists. following the erase of the user space, the protection block for the flash macro with the highest address range is erased. following the erase of the protection block, zeros are written into every bit of the protection table. the next lowest flash macro in the address space then has its protection block erased and filled with zeros. the end result of the eraseall function is that all user data in the flash is destroyed and the flash is left in an unprogrammed state, ready to accept one of the various write commands. the protection bits for all user data are also reset to the zero state. the parameter block values that must be set, be sides the keys, are the clock and delay values. tableread function the tableread function gives the user access to part specific data stored in the flash during manufacturing. it also returns a revision id for the die (not to be confused with the silicon id). the table space for the cyrf69213 is simply a 64-byte row broken up into eight tables of eight bytes. the tables are numbered zero through seven. all user and hidden blocks in the cyrf69213 parts consist of 64 bytes. an internal table holds the silicon id and returns the revision id. the silicon id is returned in sram, while the revision id is returned in the cpu_a and cpu_x registers. the silicon id is a value placed in the table by programming the flash and is controlled by cypress semiconductor product engineering. the revision id is hard coded into the srom. the revision id is discussed in more detail later in this section. an internal table holds alternate trim values for the device and returns a one-byte internal revision counter. the internal revision counter starts out with a value of zero and is incremented each time one of the other revision numbers is not incremented. it is reset to zero each time one of the other revision numbers is incremented. the internal revision count is returned in the cpu_a register. the cpu_x register is always set to ffh when trim values are read. the blockid value, in the parameter block, is used to indicate which table should be returned to the user. only the three least significant bits of the blockid parameter are used by the tableread function for the cyrf69213. the upper five bits are ignored. when the function is called, it transfers bytes from the table to sram addresses f8h?ffh. the m8c?s a and x registers are used by the tableread function to return the die?s revision id. the revision id is a 16-bit value hard coded into the srom that uniquely identifies the die?s design. checksum function the checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single flash macro (bank) starting from block zero. the blockid parameter is used to pass in the number of bl ocks to calculate the checksum over. a blockid value of 1 calculates the checksum of only block 0, while a blockid value of 0 calculates the checksum of all 256 user blocks. the 16-bit checksum is returned in key1 and key2. the parameter key1 holds t he lower eight bits of the checksum and the parameter key2 holds the upper eight bits of the checksum. the checksum algorithm executes the following sequence of three instructions over the number of blocks times 64 to be checksummed. romx add [key1], a adc [key2], 0 table 32. eraseall parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed clock 0,fch clock divider used to set the write pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 33. table read parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed blockid 0,fah table number to read table 34. checksum parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed blockid 0,fah number of fl ash blocks to calculate checksum on
cyrf69213 document number: 001-07552 rev. *g page 24 of 85 srom table read description figure 7. srom table the silicon ids for encore ii devices are stored in srom tables in the part, as shown in figure 7 . the silicon id can be read out from the part using srom table reads. this is demonstrated in the following pseudo code. as mentioned in the section srom on page 20 , the srom variables occupy address f8h through ffh in the sram. each of the variables and their definition in given in the section srom on page 20 . area sscparmblka(ram,abs) org f8h // variables are defined starting at address f8h ssc_key1: ; f8h supervisory key ssc_returncode: blk 1 ; f8h result code ssc_key2 : blk 1 ;f9h supervisory stack ptr key ssc_blockid: blk 1 ; fah block id ssc_pointer: blk 1 ; fbh pointer to data buffer ssc_clock: blk 1 ; fch clock ssc_mode: blk 1 ; fdh clockw clocke multiplier ssc_delay: blk 1 ; feh flash macro sequence delay count ssc_write_resultcode: blk 1 ; ffh temporary result code _main: mov a, 0 mov [ssc_blockid], a// to read from table 0 - silicon id is stored in table 0 //call srom operation to read the srom table mov x, sp ; copy sp into x mov a, x ; a temp stored in x add a, 3 ; create 3 byte stack frame (2 + pushed a) mov [ssc_key2], a ; save stack frame for supervisory code ; load the supervisory code for flash operations mov [ssc_key1], 3ah ;flash_oper_key - 3ah mov a,6 ; load a with specific operation. 06h is the code for table read table 24 ssc ; ssc call the supervisory rom // at the end of the ssc command the silicon id is stored in f8 (msb) and f9(lsb) of the sram .terminate: jmp .terminate f8h table 0 table 1 table 2 table 3 table 4 table 5 table 6 table 7 f9h f8h f8h f8h f8h f8h f8h silicon id [15-8] silicon id [7-0]
cyrf69213 document number: 001-07552 rev. *g page 25 of 85 clocking the cyrf69213 internal oscillator outputs two frequencies, the internal 24 mhz oscillator and the 32 khz low power oscillator. the internal 24 mhz oscillator is designed such that it may be trimmed to an output frequency of 24 mhz over temperature and vo ltage variation. with the presence of usb traffic, the internal 24 mh z oscillator can be set to precisely tune to usb timing requirem ents (24 mhz 1.5%). without usb traffic, the internal 24 mhz oscillator accuracy is 24 mhz 5% (between 0 c?70 c). no external components are required to achieve this level of accuracy. the internal low speed oscillator of nominally 32 khz provides a slow clock source for the cyrf69213 in suspend mode, particula rly to generate a periodic wakeup interrupt and also to provide a cl ock to sequential logic during power up and power down events w hen the main clock is stopped. in addition, this oscillator can also be used as a clocking source for the interval timer clock (itm rclk) and capture timer clock (tcapclk). the 32 khz low power oscillator can operate in low power mode or can provide a more accurate clock in normal mode. the internal 32 khz low power oscillator accuracy ranges (between 0 c?70 c) as follows: 5 v normal mode: ?8% to + 16% 5 v lp mode: +12% to + 48% when using the 32 khz oscillator the pitmrl/h should be read until two consecutive readings match before sending/receiving data . the following firmware example assumes the developer is interested in the lower byte of the pit. read_pit_counter: mov a, reg[pitmrl] mov [57h], a mov a, reg[pitmrl] mov [58h], a mov [59h], a mov a, reg{pitmrl] mov [60h], a ;;;start comparison mov a, [60h] mov x, [59h] sub a, [59h] jz done mov a, [59h] mov x, [58h] sub a, [58h] jz done mov x, [57h] ;;;correct data is in memory location 57h done: mov [57h], x ret
cyrf69213 document number: 001-07552 rev. *g page 26 of 85 clock architecture description the cyrf69213 clock selection circuitry allows the selection of independent clocks for the cpu, usb, interval timers, and capture timers. the cpu clock, cpuclk, can be sourced from the internal 24 mhz oscillator. this clock source can optionally be divided by 2 n where n is 0?5,7 (see table 38 on page 29 ). usbclk, which must be 12 mhz for the usb sie to function properly, can be sourced by the internal 24 mhz oscillator. an optional divide-by-two allows the use of the 24 mhz source. the interval timer clock (itmrclk), can be sourced from the internal 24 mhz oscillator, the internal 32 khz low power oscillator, except when in sleep mode, or from the timer capture clock (tcapclk). a programmable prescaler of 1, 2, 3, 4 then divides the selected source. the timer capture clock (tcapclk) can be sourced from the internal 24 mhz oscillator, or the internal 32 khz low power oscillator except when in sleep mode. the clkout pin (p0.1) can be driven from one of many sources. this is used for test and can also be used in some applications. the sources that can drive the clkout are: clkin after the optional eftb filter internal 24 mhz oscillator internal 32 khz low power oscillator except when in sleep mode cpuclk after the programmable divider figure 8. clock block diagram cpu_clk 24 mhz mux clk_usb sel scale clk_24mhz cpuclk sel mux scale (divide by 2 n , n = 0-5,7) clk_32 khz lp osc 32 khz sel scale out 0x 12 mhz 0x 12 mhz 1 1 reserved 11 reserved
cyrf69213 document number: 001-07552 rev. *g page 27 of 85 table 35. iosc trim (iosctr) [0x34] [r/w] bit # 7 6 5 4 3 2 1 0 field foffset[2:0] gain[4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 d d d d d the i/osc calibrate register is used to calibrate the internal oscillator. the reset value is undefined, but during boot the sr om writes a calibration value that is determined during manufacturing test. this value should not require change during normal use . this is the meaning of ?d? in the default field bits 7:5 foffset [2:0] this value is used to trim the frequency of the internal oscill ator. these bits are not used in factory calibration and is zero . setting each of these bits causes the appropri ate fine offset in oscillator frequency foffset bit 0 = 7.5 khz foffset bit 1 = 15 khz foffset bit 2 = 30 khz bits 4:0 gain [4:0] the effective frequency change of the offset input is controlled through the gain input. a lower value of the gain setting incr eases the gain of the offset input. this value sets the size of each offset step for the internal oscillator. nominal gain change (kh z/off- setstep) at each bit, typical conditions (24 mhz operation): gain bit 0 = ?1.5 khz gain bit 1 = ?3.0 khz gain bit 2 = ?6 khz gain bit 3 = ?12 khz gain bit 4 = ?24 khz table 36. lposc trim (lposctr) [0x36] [r/w] bit # 7 6 5 4 3 2 1 0 field 32 khz low power reserved 32 khz bias trim [1:0] 32 khz freq trim [3:0] read/write r/w ? r/w r/w r/w r/w r/w r/w default 0 d d d dd d d this register is used to calibrate the 32 khz low speed oscilla tor. the reset value is undefined, but during boot the srom writ es a calibration value that is determined during manufacturing test . this value should not require change during normal use. this is the meaning of ?d? in the default field. if the 32 khz low power bit needs to be written, care should be taken not to disturb t he 32 khz bias trim and the 32 khz freq trim fields from their factory calibrated values bit 7 32 khz low power 0 = the 32 khz low speed oscillator operates in normal mode 1 = the 32 khz low speed oscillator operates in a low power mode. the oscillator continues to function normally but with re- duced accuracy bit 6 reserved bits 5:4 32 khz bias trim [1:0] these bits control the bias current of the low power oscillator. 0 0 = mid bias 0 1 = high bias 1 0 = reserved 1 1 = reserved important note do not program the 32 khz bias trim [1:0] field with the re served 10b value, as the oscillator does not oscillate at all corner conditions with this setting bits 3:0 32 khz freq trim [3:0] these bits are used to trim the frequency of the low power oscillator
cyrf69213 document number: 001-07552 rev. *g page 28 of 85 table 37. cpu/usb clock co nfig cpuclkcr) [0x30] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved read/write ? r/w r/w ? ? ? ? r/w default 0 0 0 0 0 0 0 0 bit 7 reserved bit 6 reserved bit 5 reserved bits 4:1 reserved bit 0 reserved note the cpu speed selection is configured using the osc_cr0 register ( table 38 on page 29 )
cyrf69213 document number: 001-07552 rev. *g page 29 of 85 table 38. osc control 0 (osc_cr0) [0x1e0] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved no buzz sleep timer [1:0] cpu speed [2:0] read/write ? ? r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bits 7:6 reserved bit 5 no buzz during sleep (the sleep bit is set in the cpu_scr register ? table 42 on page 33 ), the lvd and por detection circuit is turned on periodically to detect any por and lvd events on the v cc pin (the sleep duty cycle bits in the eco_tr are used to control the duty cycle ? table 46 on page 38 ). to facilitate the detection of por and lvd events, the no buzz bit is used to force the lvd and por detection circuit to be continuously enabled during sleep. this results in a faster response to an lvd or por event during sleep at the expense of a slightly higher than average sleep current 0 = the lvd and por detection circuit is turned on periodically as configured in the sleep duty cycle 1 = the sleep duty cycle value is overridden. the lvd and por detection circuit is always enabled note the periodic sleep duty cycle enabling is independent with the sleep interval shown in the sleep [1:0] bits below bits 4:3 sleep timer [1:0] note sleep intervals are approximate bits 2:0 cpu speed [2:0] the cyrf69213 may operate over a range of cpu clock speeds. the reset value for the cpu speed bits is zero; therefore, the default cpu speed is one-eighth of the internal 24 mhz, or 3 mhz regardless of the cpu speed bit?s setting, if the actual cpu sp eed is greater than 12 mhz, the 24 mhz operating requirements apply. the operating voltage requirements are not relaxed until the cpu speed is at 12 mhz or less important note correct usb operations require the cpu clock speed be at least 1.5 mhz or not less than usb clock/8. if the two clocks have the same source then the cpu clock divider shou ld not be set to divide by more than 8. if the two clocks have diffe rent sources, care must be taken to ensure that the maximum ratio of usb clock/cpu clock can never exceed 8 across the full specification range of both clock sources sleep timer [1:0] sleep timer clock frequency (nominal) sleep period (nominal) watchdog period (nominal) 00 512 hz 1.95 ms 6 ms 01 64 hz 15.6 ms 47 ms 10 8 hz 125 ms 375 ms 11 1 hz 1 sec 3 sec cpu speed [2:0] cpu 000 3 mhz (default) 001 6 mhz 010 12 mhz 011 24 mhz 100 1.5 mhz 101 750 khz 110 187 khz 111 reserved
cyrf69213 document number: 001-07552 rev. *g page 30 of 85 table 39. usb osclock clock config uration (osclckcr) [0x39] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved fine tune only usb osclock disable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 0 0 0 0 this register is used to trim the internal 24 mhz oscillator using received low speed usb packets as a timing reference. the us b osclock circuit is active when the internal 24 mhz oscillator provides the usb clock bits 7:2 reserved bit 1 fine tune only 0 = enable 1 = disable the oscillator lock from performing the course-tune portion of its retuning. the oscillator lock must be allowed to perform a course tuning to tune the oscillator for correct usb sie operation. after the oscillator is properly tuned this bit c an be set to reduce variance in the internal oscillator frequency that would be caused by course tuning bit 0 usb osclock disable 0 = enable. with the presence of usb traffic, the internal 24 mhz oscillator precisely tunes to 24 mhz 1.5% 1 = disable. the internal 24 mhz oscillator is not trimmed based on usb packets. this setting is useful when the internal oscil - lator is not sourcing the usbsie clock table 40. timer clock conf ig (tmrclkcr) [0x31] [r/w] bit # 7 6 5 4 3 2 1 0 field tcapcl divider tcapclk select itmrclk divider itmrclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default - - - - 1 1 0 0 bits 7:6 tcapclk divider tcapclk divider controls the tcapclk divisor 00 = divide by 2 01 = divide by 4 10 = divide by 6 11 = divide by 8 bits 5:4 tcapclk select the tcapclk select field controls the source of the tcapclk 0 0 = internal 24 mhz oscillator 0 1 = reserved) 1 0 = internal 32 khz low power oscillator. however this configuration is not used in sleep mode. 1 1 = tcapclk disabled note the 1024- ? s interval timer is based on the assumption that tcapclk is running at 4 mhz. changes in tcapclk frequency causes a corresponding change in the 1024 ? s interval timer frequency bits 3:2 itmrclk divider itmrclk divider controls the itmrclk divisor. 0 0 = divider value of 1 0 1 = divider value of 2 1 0 = divider value of 3 1 1 = divider value of 4 bits 1:0 itmrclk select 0 0 = internal 24 mhz oscillator 0 1 = reserved 1 0 = internal 32 khz low power oscillator. however this configuration is not used in sleep mode. 1 1 = tcapclk
cyrf69213 document number: 001-07552 rev. *g page 31 of 85 interval timer clock (itmrclk) the interval timer clock (itmrclk) can be sourced from the internal 24 mhz oscillator, the internal 32 khz low power oscillator except when in sleep mode, or the timer capture clock. a programmable prescaler of 1, 2, 3, or 4 then divides the selected source. the 12-bit programmable interval timer is a simple down counter with a programmable reload value. it provides a 1 ? s resolution by default. when the down counter reaches zero, the next clock is spent reloading. the reload value can be read and written while the counter is running, but care should be taken to ensure that the counter does not unintentionally reload while the 12-bit reload value is only partially stored ? for example, between the two writes of the 12-bit value. the programmable interval timer generates an interrupt to the cpu on each reload. the parameters to be set appears on the device editor view of psoc designer after you place the cyrf69213 timer user module. the parameters are pitimer_source and pitimer_divider. the pitimer_sour ce is the clock to the timer and the pitmer_divider is the value the clock is divided by. the interval register (pitmr) holds the value that is loaded into the pit counter on terminal count. the pit counter is a down counter. the programmable interval timer resolution is configurable. for example: tcapclk divide by x of cpu clock (for example tcapclk divide by 2 of a 24 mhz cpu clock gives a frequency of 12 mhz) itmrclk divide by x of tcapclk (for example, itmrclk divide by 3 of tcapclk is 4 mhz so resolution is 0.25 ? s) timer capture clock (tcapclk) the timer capture clock can be sourced from the internal 24 mhz oscillator or the internal 332 khz low power oscillator except when in sleep mode. a programmable prescaler of 2, 4, 6, or 8 then divides the selected source. figure 9. programmable inte rval timer block diagram system clock clock timer configuration status and control 12-bit reload value 12-bit down counter 12-bit reload counter interrupt c ontroller
cyrf69213 document number: 001-07552 rev. *g page 32 of 85 figure 10. timer ca pture block diagram cpu clock during sleep mode when the cpu enters sleep mode the cpuclk select (bit [0], ta b l e 3 7 ) is forced to the internal oscillator, and the oscillator is stopped. when the cpu comes out of sleep mode it is running on the internal oscillator. the internal oscillator recovery time is three clock cycles of the intern al 32 khz low power oscillator. reset the microcontroller supports two types of resets: power on reset (por) and watchdog reset (wdr). when reset is initiated, all registers are restored to their default states and all interrupts are disabled. the occurrence of a reset is recorded in the system status and control register (cpu_scr). bits within this register record the occurrence of por and wdr reset respectively. the firmware can interrogate these bits to determine the cause of a reset. the microcontroller resumes execution from flash address 0x0000 after a reset. the internal clocking mode is active after a reset. note the cpu clock defaults to 3 mhz (internal 24 mhz oscillator divide-by-8 mode) at por to guarantee operation at the low v cc that might be present during the supply ramp. 16-bit counter configuration status and control prescale mux capture registers interrupt controller 1ms timer overflow interrupt captimer clock system clock capture0 int capture1 int table 41. clock i/o config (clkiocr) [0x32] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved clkout select read/write ? ? ???? r/w r/w default 0 0 0000 0 0 bits 7:2 reserved bits 1:0 clkout select 0 0 = internal 24 mhz oscillator 0 1 = reserved 1 0 = internal 32 khz low power oscillator.however this configuration is not used in sleep mode. 1 1 = cpuclk
cyrf69213 document number: 001-07552 rev. *g page 33 of 85 table 42. system status and control register (cpu_scr) [0xff] [r/w] bit # 7 6 5 4 3 2 1 0 field gies reserved wdrs pors sleep reserved stop read/write r ? r/c [3] r/c [3] r/w ? ? r/w default 0 0 0 1 00 0 0 t he bits of the cpu_scr register are used to convey status and control of events for various functions of an cyrf69213 device bit 7 gies the global interrupt enable status bit is a read only status bit and its use is discouraged. the gies bit is a legacy bit, whic h was used to provide the ability to read the gie bit of the cpu_f register. however, the cpu_f register is now readable. when this bit is set, it indicates that the gie bit in the cpu_f register is also set which, in turn, indicates that the microprocessor s ervices interrupts 0 = global interrupts disabled 1 = global interrupt enabled bit 6 reserved bit 5 wdrs the wdrs bit is set by the cpu to indicate that a wdr event has occurred. the user can read this bit to determine the type of reset that has occurred. the user can clear but not set this bit 0 = no wdr 1 = a wdr event has occurred bit 4 pors the pors bit is set by the cpu to indicate that a por event ha s occurred. the user can read this bit to determine the type of reset that has occurred. the user can clear but not set this bit 0 = no por 1 = a por event has occurred. (note that wdr events does not occur until this bit is cleared) bit 3 sleep set by the user to enable cpu sleep state. cpu remains in sleep mode until any interrupt is pending. the sleep bit is covered in more detail in the sleep mode section 0 = normal operation 1 = sleep bit 2:1 reserved bit 0 stop this bit is set by the user to halt the cpu. the cpu remains ha lted until a reset (wdr, por, or external reset) has taken place . if an application wants to stop code execution until a reset, the preferred method would be to use the halt instruction rather than writing to this bit 0 = normal cpu operation 1 = cpu is halted (not recommended) note 3. c = clear. this bit can only be cleared by the user and cannot be set by firmware
cyrf69213 document number: 001-07552 rev. *g page 34 of 85 power on reset por occurs every time the power to the device is switched on. por is released when the supply is typically 2.6 v for the upward supply transition, with typically 50 mv of hysteresis during the power on transient. bit 4 of the system status and control register (cpu_scr) is set to record this event (the register contents are set to 00010000 by the por). after a por, the microprocessor is held off for approximately 20 ms for the v cc supply to stabilize before executing the first instruction at address 0x00 in the flash. if the v cc voltage drops below the por downward supply trip point, por is reasserted. the v cc supply needs to ramp linearly from 0 to 4 v in 0 to 200 ms. important the pors status bit is set at por and can only be cleared by the user. it cannot be set by firmware. watchdog timer reset the user has the option to enable the wdt. the wdt is enabled by clearing the pors bit. when the pors bit is cleared, the wdt cannot be disabled. the only exception to this is if a por event takes place, which disables the wdt. the sleep timer is used to generate the sleep time period and the watchdog time period. the sleep timer is clocked by the internal 32 khz low power oscillator system clock. the user can program the sleep time period using the sleep timer bits of the osc_cr0 register ( table 38 on page 29 ). when the sleep time elapses (sleep timer overflows), an interrupt to the sleep timer interrupt vector is generated. the watchdog timer period is automatically set to be three counts of the sleep timer overflows. this represents between two and three sleep intervals depending on the count in the sleep timer at the previous wdt clear. when this timer reaches three, a wdr is generated. the user can either clear the wdt, or the wdt and the sleep timer. whenever the user writes to the reset wdt register (res_wdt), the wdt is cleared. if the data that is written is the hex value 0x38, the sleep timer is also cleared at the same time. sleep mode the cpu can only be put to sleep by the firmware. this is accom- plished by setting the sleep bit in the system status and control register (cpu_scr). this stops the cpu from executing instructions, and the cpu remains asleep until an interrupt comes pending, or there is a reset event (either a power on reset, or a watchdog timer reset). the low voltage detection circuit (lvd) drops into fully functional power reduced states, and the latency for the lvd is increased. the actual latency can be traded against power consumption by changing the sleep duty cycle field of the eco_tr register. the internal 32 khz low speed oscillator remains running. prior to entering suspend mode, firmware can optionally configure the 32 khz low speed oscillator to operate in a low power mode to help reduce the overall power consumption (using bit 7, table 36 on page 27 ). this helps save approximately 5 ? a; however, the trade off is that the 32 khz low speed oscillator is less accurate. all interrupts remain active. only the occurrence of an interrupt wakes the part from sleep. the stop bit in the system status and control register (cpu_scr) must be cleared for a part to resume out of sleep. the global interrupt enable bit of the cpu flags register (cpu_f) does not have any effect. any unmasked interrupt wakes the system up. as a result, any interrupts not intended for waking must be disabled through the interrupt mask registers. when the cpu exits sleep mode the cpuclk select (bit 1, table 37 on page 28 ) is forced to the internal oscillator. the internal oscillator recovery time is three clock cycles of the internal 32 khz low power oscillator. the internal 24 mhz oscillator restarts immediately on exiting sleep mode. on exiting sleep mode, when the clock is stable and the delay time has expired, the instruction immediately following the sleep instruction is executed before the interrupt service routine (if enabled). the sleep interrupt allows the microcontroller to wake up periodically and poll system components while maintaining very low average power consumption. the sleep interrupt may also be used to provide periodic interrupts during non sleep modes. sleep sequence the sleep bit is an input into the sleep logic circuit. this circuit is designed to sequence the device into and out of the hardware sleep state. the hardware sequence to put the device to sleep is shown in figure 11 and is defined as follows. 1. firmware sets the sleep bit in the cpu_scr0 register. the bus request (brq) signal to the cpu is immediately asserted. this is a request by the system to halt cpu operation at an instruction boundary. the cpu samples brq on the positive edge of cpuclk. 2. due to the specific timing of the register write, the cpu issues a bus request acknowledge (bra) on the following positive edge of the cpu clock. the sleep logic waits for the following negative edge of the cpu clock and then asserts a system-wide power down (pd) signal. in figure 11 the cpu is halted and the system-wide po wer down signal is asserted. 3. the system-wide pd (power dow n) signal controls several major circuit blocks: the flash memory module, the internal table 43. reset watchdog timer (reswdt) [0xe3] [w] bit # 7 6 5 4 3 2 1 0 field reset watchdog timer [7:0] read/write w w w w ww w w default 0 0 0 0 00 0 0 any write to this register clears watchdog timer, a write of 0x38 also clears the sleep timer bits 7:0 reset watchdog timer [7:0]
cyrf69213 document number: 001-07552 rev. *g page 35 of 85 24 mhz oscillator, the eftb filter and the bandgap voltage reference. these circuits transition into a zero power state. the only operational circuits on chip are the low power oscillator, the bandgap refresh circuit, and the supply voltage monitor (por/lvd) circuit. note to achieve the lowest possible power consumption during suspend/sleep, the following conditions must be observed in addition to considerations for the sleep timer. all gpios must be set to outputs and driven low the usb pins p1.0 and p1.1 should be configured as inputs with their pull ups enabled. figure 11. sleep timing wakeup sequence when asleep, the only event that can wake the system up is an interrupt. the global interrupt enable of the cpu flag register does not need to be set. any unmasked interrupt wakes the system up. it is optio nal for the cpu to actually take the interrupt after the wakeup sequence. the wakeup sequence is synchronized to the 32 khz clock for purposes of sequencing a startup delay, to allow the flash memory module enough time to power up before the cpu asserts the first read access. another reason for the delay is to allow the oscillator, bandgap, and lvd/por circuits time to settle before actually being used in the system. as shown in figure 12 on page 36 , the wakeup sequence is as follows: 1. the wakeup interrupt occurs and is synchronized by the negative edge of the 32 khz clock. 2. at the following positive edge of the 32 khz clock, the system-wide pd signal is negated. the flash memory module, internal oscillator, eftb, and bandgap circuit are all powered up to a normal operating state. 3. at the following positive edge of the 32 khz clock, the current values for the precision por and lvd have settled and are sampled. 4. at the following negative edge of the 32 khz clock (after about 15 s nominal), the brq signal is negated by the sleep logic circuit. on the following cpuclk, bra is negated by the cpu and instruction execution resumes. note that in figure 12 on page 36 fixed function blocks, such as flash, internal oscillator, eftb, and bandgap, have about 15 s start up. the wakeup times (interrupt to cpu operational) ranges from 75 s to 105 s. low power in sleep mode the following steps are mandat ory before confi guring the system into suspend mode to meet the specifications: 1. clear p11cr[0], p10cr[0] - during usb and non-usb operations 2. clear the usb enable usbcr[7] - during usb mode operations 3. set p10cr[1] - during non-usb mode operations 4. to avoid current consumption make sure itmrclk, tcpclk, and usbclk are not sourced by either low power 32khz oscillator or 24 mh z crystal-less oscillator. all the other blocks go to the power down mode automatically on suspend. firmware write to scr sleep bit causes an immediate brq iow sleep brq pd bra cpuclk cpu captures brq on next cpuclk edge cpu responds with a bra on the falling edge of cpuclk, pd is asserted. the 24/48 mhz system clock is halted; the flash and bandgap are powered down
cyrf69213 document number: 001-07552 rev. *g page 36 of 85 the following steps are user configurable and help in reducing the average suspend mode power consumption. 1. configure the power supply monitor at a large r egular intervals, control register bits are 1,eb[7:6] (power system sleep duty cycle pssdc[1:0]). 2. configure the low power oscillator into low power mode, control register bit is lopsctr[7]. figure 12. wakeup timing int sleep pd lvd ppor bandgap clk32k sample sample lvd/por cpuclk/ 24mhz bra brq enable cpu (not to scale) sleep timer or gpio interrupt occurs interrupt is double sampled by 32k clock and pd is negated to system cpu is restarted after 90 ms (nominal)
cyrf69213 document number: 001-07552 rev. *g page 37 of 85 low voltage detect control por compare state table 44. low voltage control register (lvdcr) [0x1e3] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved porlev[1:0] reserved vm[2:0] read/write ? ? r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the configuration of the power on reset/low voltage detection block bits 7:6 reserved bits 5:4 porlev[1:0] this field controls the level below which the precis ion power-on-reset (ppor) detector generates a reset 0 0 = 2.7 v range (trip near 2.6 v) 0 1 = 3 v range (trip near 2.9 v) 1 0 = 5 v range, > 4.75 v (trip near 4.65 v). this setting must be used when operating the cpu above 12 mhz. 1 1 = ppor does not generate a reset, but values read from the voltage monitor comparators register ( table 45 ) give the in- ternal ppor comparator state with trip point set to the 3 v range setting bit 3 reserved bits 2:0 vm[2:0] this field controls the level below which the low voltage-detect trips ? possibly generating an interrupt and the level at whic h the flash is enabled for operation . vm[2:0] lvd trip point (v) min. typical max. 000 reserved reserved reserved 001 reserved reserved reserved 010 reserved reserved reserved 011 reserved reserved reserved 100 4.439 4.48 4.528 101 4.597 4.64 4.689 110 4.680 4.73 4.774 111 4.766 4.82 4.862 table 45. voltage monitor comparators register (vltcmp) [0x1e4] [r] bit # 7 6 5 4 3 2 1 0 field reserved lvd ppor read/write ? ? ? ? ?? r r default 0 0 0 0 00 0 0 this read-only register allows reading the current state of t he low voltage-detection and prec ision-power-on-reset comparators bits 7:2 reserved bit 1 lvd this bit is set to indicate that the low voltage-detect comparat or has tripped, indicating that the supply voltage has gone bel ow the trip point set by vm[2:0] (see table 44 ) 0 = no low voltage-detect event 1 = a low voltage-detect has tripped bit 0 ppor this bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply voltage is bel ow the trip point set by porlev[1:0] 0 = no precision-power-on-reset event 1 = a precision-power-on-reset event has tripped
cyrf69213 document number: 001-07552 rev. *g page 38 of 85 eco trim register general-purpose i/o ports the general purpose i/o ports are discussed in the following sections. port data registers table 46. eco (eco_tr) [0x1eb] [r/w] bit # 7 6 5 4 3 2 1 0 field sleep duty cycle [1:0] reserved read/write r/w r/w ? ? ? ? ? ? default 0 0 0 0 00 0 0 this register controls the ratios (in numbers of 32 khz clock periods) of ?on? time versus ?off? time for lvd and por detection circuit bits 7:6 sleep duty cycle [1:0] 0 0 = 1/128 periods of the internal 32 khz low speed oscillator 0 1 = 1/512 periods of the internal 32 khz low speed oscillator 1 0 = 1/32 periods of the internal 32 khz low speed oscillator 1 1 = 1/8 periods of the internal 32 khz low speed oscillato r table 47. p0 data register (p0data)[0x00] [r/w] bit # 7 6 5 4 3 2 1 0 field p0.7 reserved reserved p0.4/int2 p 0.3/int1 reserved p0.1 reserved read/write r/w r/w r/w r/w r/w r/w r/w r/w default 00000000 this register contains the data for port 0. writing to this register sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 0 pins bit 7 p0.7 data bits 6:5 reserved the use of the pins as the p0.6?p0.5 gpios and the alternative functions exist in the cyrf69213 bits 4:3 p0.4?p0.3 data/int2 ? int1 in addition to their use as the p0.4?p0.3 gpios, these pins can also be used for the alternative functions as the interrupt pin s (int0?int2). to configure the p0.4?p0.3 pins, refer to the p0.3/int1?p0.4/int2 configuration register ( table 51 ) the use of the pins as the p0.4?p0.3 gpios and the alternative functions exist in the cyrf69213 bit 2 reserved bit 1 p0.1 bit 0 reserved
cyrf69213 document number: 001-07552 rev. *g page 39 of 85 gpio port configuration all the gpio configuration registers have common configuration controls. the following are the bit definitions of the gpio configuration registers. int enable when set, the int enable bit allows the gpio to generate interrupts. interrupt generate can occur regardless of whether the pin is configured for input or output. all interrupts are edge sensitive, however for any interrupt that is shared by multiple sources (that is, ports 2, 3, and 4) all inputs must be deasserted before a new interrupt can occur. when clear, the corresponding interrupt is disabled on the pin. it is possible to configure gpios as outputs, enable the interrupt on the pin and then to generate the interrupt by driving the appropriate pin state. this is useful in test and may have value in applications as well. int act low when set, the corresponding interrupt is active on the falling edge. when clear, the corresponding interrupt is active on the rising edge. ttl thresh when set, the input has ttl threshold. when clear, the input has standard cmos threshold. high sink when set, the output can sink up to 50 ma. when clear, the output can sink up to 8 ma. on the cyrf69213, only the p1.7?p1.3 have 50 ma sink drive capability. other pins have 8 ma sink drive capability. open drain when set, the output on the pin is determined by the port data register. if the corresponding bit in the port data register is set, table 48. p1 data register (p1data) [0x01] [r/w] bit # 7 6 5 4 3 2 1 0 field p1.7 p1.6/smiso p1.5/smosi p1.4/scl k p1.3/ssel p1.2/vr eg p1.1/d? p1.0/d+ read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 1. writing to this register sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 1 pins bit 7 p1.7 data bits 6:3 p1.6?p1.3 data/spi pins (smiso, smosi, sclk, ssel) in addition to their use as the p1.6?p1.3 gpios, these pins can also be used for the alternative function as the spi interface pins. to configure the p1.6?p1.3 pins, refer to the p1.3?p1.6 configuration register ( table 56 on page 43 ) the use of the pins as the p1.6?p1.3 gpios and the alternative functions exist in all the cyrf69213 parts bit 2 p1.2/vreg this pin is used as the regulator output. the 3.3 v vreg output must be enabled by setting bit 0 of vregcr register ( table 80 on page 56 ). a 1 mf min, 2 mf max capacitor is required on vreg output. bits 1:0 p1.1?p1.0/d? and d+ when usb mode is disabled (bit 7 in table 81 on page 57 is clear), the p1.1 and p1.0 bits are used to control the state of the p1.0 and p1.1 pins. when the usb mode is enabled, the p1.1 and p1.0 pins are used as the d? and d+ pins, respectively. if the usb force state bit (bit 0 in table 79 on page 56 ) is set, the state of the d? and d+ pins can be controlled by writing to the d? and d+ bits table 49. p2 data register (p2data) [0x02] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved p2.1?p2.0 read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 2. writing to this register sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 2 pins bits 7:2 reserved data [7:2] bits 1:0 p2 data [1:0]
cyrf69213 document number: 001-07552 rev. *g page 40 of 85 the pin is in high impedance state. if the corresponding bit in the port data register is clear, the pin is driven low. when clear, the output is driven low or high. pull up enable when set the pin has a 7k pull up to v cc (or vreg for ports with v3.3 enabled). when clear, the pull up is disabled. output enable when set, the output driver of the pin is enabled. when clear, the output driver of the pin is disabled. for pins with shared functions there are some special cases. vreg output/spi use the p1.2 (vreg), p1.3 (ssel) , p1.4 (sclk), p1.5 (smosi) and p1.6 (smiso) pins can be used for their dedicated functions or for gpio. to enable the pin for gpio, clear the corresponding vreg output or spi use bit. the spi function controls the output enable for its dedicated function pins when their gpio enable bit is clear. 3.3 v drive the p1.3 (ssel), p1.4 (scl k), p1.5 (smosi) and p1.6 (smiso) pins have an alternate voltage source from the voltage regulator. if the 3.3 v drive bit is set a high level is driven from the voltage regulator instead of from v cc . setting the 3.3 v drive bit does not enable the voltage regulator. that must be done explicitly by setting the vreg enable bit in the vregcr register ( table 80 on page 56 ). figure 13. block diagram of a gpio v cc vreg v cc vreg gpio pin r up data out v cc gnd vreg gnd 3.3v drive pull-up enable output enable open drain port data high sink data in ttl threshold table 50. p0.1 configuration (p01cr) [0x06] r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull up enable output enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this register is used to configure p0.1 in the cyrf69213, only 8 ma sink drive capability is available on this pin regardless o f the setting of the high sink bit bit 7: reserved
cyrf69213 document number: 001-07552 rev. *g page 41 of 85 table 51. p0.3/int1?p0.4/int2 configuration (p03cr?p04cr) [0x08?0x09] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int act low ttl thresh reserved open drain pull up enable output enable read/write ? ? r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 t hese registers control the operation of pins p0.3?p0.4, respec tively. these pins are shared between the p0.3?p0.4 gpios and the int0?int2. these registers exist in all cyrf69213 parts. the int0?int2 interrupts are different than all the other gpio interrupts. these pins are connected directly to the interrupt controller to provide three edge-sensitive interrupts with indep endent interrupt vectors. these interrupts occur on a rising edge when int act low is clear and on a falling edge when int act low is set. these pins are enabled as interrupt source s in the interrupt controller registers ( ta b l e 7 7 and table 75 ) to use these pins as interrupt inputs configure them as inputs by clearing the corresponding output enable. if the int0?int2 pi ns are configured as outputs with interrupts enabled, firmware can gene rate an interrupt by writing the appropriate value to the p 0.3 and p0.4 data bits in the p0 data register regardless of whether the pins are used as interrupt or gpio pins the int enable, int act low, ttl threshold, open drain, and p ull up enable bits control the behavior of the pin the p0.3/int1?p0.4/int2 pins are individually configured with the p03cr (0x08), and p04cr (0x09), respectively. note changing the state of the int act low bit can cause an unintentional interrupt to be generated. when configuring these interru pt sources, it is best to follow the following procedure: 1. disable interrupt source 2. configure interrupt source 3. clear any pending interrupts from the source 4. enable interrupt source table 52. p0.7 configuration (p07cr) [0x0c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 this register controls the operation of pin p0.7.
cyrf69213 document number: 001-07552 rev. *g page 42 of 85 table 53. p1.0/d+ configuration (p10cr) [0x0d] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved 5k pull up enable output enable read/write r/w r/w r/w ? ?? ? r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.0 (d+) pin when the usb interface is not enabled, allowing the pin to be used as a gpio pin which is pulled up. see table 81 for information on enabling usb. when usb is enabled, none of the controls in this register have any effect on the p1.0 pin note the p1.0 is an open drain only output. it can actively drive a signal low, but cannot actively drive a signal high bit 1 5k pull up enable 0 = disable the 5 kohm pull up resistors 1 = enable 5 kohm pull up resistors for both p1.0 and p1.1. enable the use of the p1.0 (d+) and p1.1 (d?) pins as pulled up gpios bit 0 this bit enables the output on p1.0/d+. this bit should be cleared in sleep mode. table 54. p1.1/d? configuration (p11cr) [0x0e] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved open drain reserved output enable read/write ? r/w r/w ? ?r/w? r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.1 (d?) pin when the usb interface is not enabled, allowing the pin to be used as a gpio. see table 81 for information on enabling usb. when usb is enabled, none of the controls in this register have any effect on the p1.1 pin. when usb is disabled, the 5 kohm pull up resistor on this pin can be enabled by the 5k pull up enable bit of t he p10cr register ( ta b l e 5 3 ) bit 0this bit enables the output on p1.1/d-. this bit should be cleared in sleep mode. note there is no 2 ma sourcing capability on this pin. the pin can only sink 5 ma at v ol3 table 55. p1.2 configuration (p12cr) [0x0f] [r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl threshold reserved open drain pull up enable output enable read/write r/w r/w r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.2 bit 7 clk output 0 = the internally selected clock is not sent out onto p1.2 pin 1 = when clk output is set, the internally selected clock is sent out onto p1.2 pin
cyrf69213 document number: 001-07552 rev. *g page 43 of 85 table 56. p1.3 configuration (p13cr) [0x10] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low 3.3 v drive high sink open drain pull up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.3 pin. this register exists in all cyrf69213 parts the p1.3 gpio?s threshold is always set to ttl when the spi hardware is enabled, the output enable and output state of the pin is controlled by the spi circuitry. when the sp i hardware is disabled, the pin is controlled by the output enable bit and the corresponding bit in the p1 data register regardless of whether the pin is used as an spi or gpio pin the int enable, int act low, 3.3 v drive, high sink, open drain, an d pull up enable control the behavior of the pin the 50 ma sink drive capability is only available in the cy7c638xx. table 57. p1.4?p1.6 configuration (p14cr?p16cr) [0x11?0x13] [r/w] bit # 7 6 5 4 3 2 1 0 field spi use int enable int act low 3.3 v drive high sink open drain pull up enable output enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 t hese registers control the operation of pins p1.4?p1.6, respectively the p1.4?p1.6 gpio?s threshold is always set to ttl when the spi hardware is enabled, pins that are configured as spi use have their output enable and output state controlled by t he spi circuitry. when the spi hardware is disabled or a pin has its spi use bit clear, the pin is controlled by the output enable bit and the corresponding bit in the p1 data register regardless of whether any pin is used as an spi or gpio pin the int enable, int act low, 3.3 v drive, high sink, open drain, an d pull up enable control the behavior of the pin bit 7 spi use 0 = disable the spi alternate function. the pin is used as a gpio 1 = enable the spi function. the spi circuitry controls the output of the pin important note for comm modes 01 or 10 (spi master or spi slave, see ta b l e 6 1 ) when configured for spi (spi use = 1 and comm modes [1:0] = spi master or spi slave mode), the input/output direction of pins p1.3, p1.5, and p1.6 is set automatically by the spi logic. however, pin p1.4's input/output direction is not automatically set ; it must be explicitly set by firmware. for spi master mode, pin p1.4 must be configured as an output; for spi slave mode, pin p1.4 must be configured as an input table 58. p1.7 configuration (p17cr) [0x14] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 t his register controls the operation of pin p1.7. this register only exists in cy7c638xx the 50 ma sink drive capability is only available in the cy7c638xx. the p1.7 gpio?s threshold is always set to ttl
cyrf69213 document number: 001-07552 rev. *g page 44 of 85 gpio configurations for low power mode: to ensure low power mode, unbonded gpio pins in cyrf69213 must be placed in a non floating state. the following assembly code snippet shows how this is achieved. this snippet can be added as a part of the initialization routine. //code snippet for addressing unbonded gpios mov a, 00h mov reg[1fh],a mov a, 01h mov reg[16h],a // port3 configuration register - enable ouptut mov a, 00h mov reg[03h],a // asserting p3.0 and p3.1 outputs to '0' mov a, 01h mov reg[05h],a // port0.0 configuration register - enable output mov reg[07h],a // port0.2 configuration register - enable output mov reg[0ah],a // port0.5 configuration register - enable output mov reg[0bh],a // port0.6 configuration register - enable output mov a,reg[00h] mov a,00h and a,9ah mov reg[00h], a // asserting outputs '0' to pins in port 1 when writing to port 0 , to access gpios p0.1,3,4,7 , mask bits 0,2,5,6 .failing to do so will void the low power. table 59. p2 configuration (p2cr) [0x15] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull up en- able output en- able read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register only exists in cy7c638xx. this register controls t he operation of pins p2.0?p2.1. in the cy7c638xx, only 8 ma sin k drive capability is available on this pin regardless of the setting of the high sink bit
cyrf69213 document number: 001-07552 rev. *g page 45 of 85 serial peripheral interface (spi) the spi master/slave interface core logic runs on the spi clock domain, making its functionality independent of system clock sp eed. spi is a four pin serial interface comprised of a clock, an enable and two data pins. figure 14. spi block diagram spi state machine ss_n data (8 bit) load empty data (8 bit) load full sclk output enable slave select output enable master in, slave out oe master out, slave in, oe shift buffer input shift buffer output shift buffer sck clock generation sck clock select sck clock phase/polarity select register block sck speed sel master/slave sel sck polarity sck phase little endian sel miso/mosi crossbar gpio block ss_n le_sel sck le_sel sck_oe ss_n_oe miso_oe mosi_oe sck sck_oe ss_n_oe sck ss_n master/slave set miso mosi miso_oe mosi_oe
cyrf69213 document number: 001-07552 rev. *g page 46 of 85 spi data register when an interrupt occurs to indicate to firmware that a byte of receive data is available, or the transmitter holding register is empty, firmware has 7 spi clocks to manage the buff ers ? to empty the receiver buffer, or to refill the transmit ho lding register. fai lure to meet this timing requirement results in incorrect data transfer. spi configure register table 60. spi data register (spidata) [0x3c] [r/w] bit # 7 6 5 4 3 2 1 0 field spidata[7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when read, this register returns the contents of the receive buffer. when written, it loads the transmit holding register bits 7:0 spi data [7:0] table 61. spi configure register (spicr) [0x3d] [r/w] bit # 7 6 5 4 3 2 1 0 field swap lsb first comm mode cpol cpha sclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 swap 0 = swap function disabled 1 = the spi block swaps its use of smosi and smiso. among other things, this can be useful in implementing single wire spi-like communications bit 6 lsb first 0 = the spi transmits and receives the msb (most significant bit) first 1 = the spi transmits and receives the lsb (least significant bit) first. bits 5:4 comm mode [1:0] 0 0: all spi communication disabled 0 1: spi master mode 1 0: spi slave mode 1 1: reserved bit 3 cpol this bit controls the spi clock (sclk) idle polarity 0 = sclk idles low 1 = sclk idles high bit 2 cpha the clock phase bit controls the phase of the clock on which data is sampled. table 62 on page 47 shows the timing for the various combinations of lsb first, cpol, and cpha bits 1:0 sclk select this field selects the speed of the master sclk. when in master mode, sclk is generated by dividing the base cpuclk important note for comm modes 01b or 10b (spi master or spi slave): when configured for spi, (spi use = 1 ? table 57 on page 43 ), the input/output direction of pins p1.3, p1.5, and p1.6 is set automatically by the spi logic. however, pin p1.4's input/output direction is not automatically set; it must be explicitly set by firmware. for spi master mode, pin p1.4 must be configured as an output; for spi slave mode, pin p1.4 must be configured as an input
cyrf69213 document number: 001-07552 rev. *g page 47 of 85 table 62. spi mode timing vs. lsb first, cpol and cpha lsb first cpha cpol diagram 000 001 010 011 100 101 110 111 sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x msb x bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb
cyrf69213 document number: 001-07552 rev. *g page 48 of 85 timer registers all timer functions of the cyrf69213 are provided by a single timer block. the timer block is asynchronous from the cpu clock. registers free-running counter the 16-bit free-running counter is clocked by a 4/6 mhz source. it can be read in software for use as a general purpose time base. when the low order byte is read, the high order byte is registered. reading the high order byte reads this register allowing the cpu to read the 16-bit value atomically (loads all bits at one time). the free-running timer generates an interrupt at a 1024 ? s rate. it can also generate an interrupt when the free-running counter overflow occurs ? every 16.384 ms. this allows extending the length of the timer in software. figure 15. 16-bit free-running counter block diagram table 63. spi sclk frequency sclk select cpuclk divisor sclk frequency cpuclk = 12 mhz cpuclk = 24 mhz 00 6 2 mhz 4 mhz 01 12 1 mhz 2 mhz 10 48 250 khz 500 khz 11 96 125 khz 250 khz timer capture clock 16-bit free running counter overflow interrupt 1024- s timer interrupt table 64. free-running timer low order byte (frtmrl) [0x20] [r/w] bit # 7 6 5 4 3 2 1 0 field free-running timer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bits 7:0 free-running timer [7:0] this register holds the low order byte of the 16-bit free-running timer. reading this register causes the high order byte to be moved into a holding register allowing an automatic read of all 16 bits simultaneously. for reads, the actual read occurs in the cycle when the low or der is read. for writes, the actual time the write occurs is the cycle when the high order is written when reading the free-running timer, the low order byte should be read first and the high order second. when writing, the low o rder byte should be written first then the high order byte table 65. free-running timer high order byte (frtmrh) [0x21] [r/w] bit # 7 6 5 4 3 2 1 0 field free-running timer [15:8] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bits 7:0 free-running timer [15:8] when reading the free-running timer, the low order byte should be read first and the high order second. when writing, the low o rder byte should be written first then the high order byte
cyrf69213 document number: 001-07552 rev. *g page 49 of 85 table 66. programmable interval timer low (pitmrl) [0x26] [r] bit # 7 6 5 4 3 2 1 0 field prog interval timer [7:0] read/write r r r r rr r r default 0 0 0 0 00 0 0 bits 7:0 ?prog interval timer [7:0] this register holds the low order byte of the 12-bit programmable interval timer. reading this register causes the high order b yte to be moved into a holding register allowing an automatic read of all 12 bits simultaneously table 67. programmable interval timer high (pitmrh) [0x27] [r] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer [11:8] read/write ? ? ? ? rr r r default 0 0 0 0 00 0 0 bits 7:4 reserved bits 3:0 prog internal timer [11:8] this register holds the high order nibble of the 12-bit programmable interval timer. reading this register returns the high ord er nibble of the 12-bit timer at the instant that the low order byte was last read table 68. programmable interval reload low (pirl) [0x28] [r/w] bit # 7 6 5 4 3 2 1 0 field prog interval [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bits 7:0 prog interval [7:0] this register holds the lower 8 bits of the timer. while writing into the 12-bit reload register, write lower byte first then t he higher nibble table 69. programmable interval reload high (pirh) [0x29] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval[11:8] read/write ? ? ? ? r/w r/w r/w r/w default 0 0 0 0 00 0 0 bits 7:4 reserved bits 3:0 prog interval [11:8] this register holds the higher 4 bits of the timer. while writing into the 12-bit reload register, write lower byte first then the higher nibble
cyrf69213 document number: 001-07552 rev. *g page 50 of 85 figure 16. 16-bit free-running counter loading timing diagram figure 17. memory mapped regi sters read/write timing diagram clk_sys write valid addr write data frt reload ready clk timer 12b prog timer 12b reload interrupt capture timer clk 16b free running counter load 16b free running counter 00a0 00a1 00a2 00a3 00a4 00a5 00a6 00a7 00a8 00a9 00ab 00ac 00ad 00ae 00af 00b0 00b1 00b2 acbe acbf acc0 16-bit free running counter loading timing 12-bit programmable timer load timing memory mapped registers read/write timing diagram clk_sys rd_wrn valid addr rdata wdata
cyrf69213 document number: 001-07552 rev. *g page 51 of 85 interrupt controller the interrupt controller and its associated registers allow the user?s code to respond to an interrupt from almost every functional block in the cyrf69213 devices. the registers associated with the interrupt controller allow interrupts to be disabled either globally or individually. the registers also provide a mechanism by which a user may clear all pending and posted interrupts, or clear individual posted or pending interrupts. the following table lists all interrupts and the priorities that are available in the cyrf69213. architectural description an interrupt is posted when its interrupt conditions occur. this results in the flip-flop in figure 18 clocking in a ?1?. the interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate int_clrx register. a posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate int_mskx register). all pending interrupts are processed by the priority encoder to determine the highest priority interrupt which is taken by the m8c if the global interrupt enable bit is set in the cpu_f register. disabling an interrupt by clearing its interrupt mask bit (in the int_mskx register) does not clear a posted interrupt, nor does it prevent an interrupt from being posted. it simply prevents a posted interrupt from becoming pending. nested interrupts can be accomplished by re-enabling interrupts inside an interrupt service routine. to do this, set the ie bit in the flag register. a block diagram of the cyrf69213 interrupt controller is shown in figure 18 . figure 18. interrupt controller block diagram table 70. interrupt numbers, priorities, vectors interrupt priority interrupt address name 0 0000h reset 1 0004h por/lvd 2 0008h int0 3 000ch spi transmitter empty 4 0010h spi receiver full 5 0014h gpio port 0 6 0018h gpio port 1 7 001ch int1 8 0020h ep0 9 0024h ep1 10 0028h ep2 11 002ch usb reset 12 0030h usb active 13 0034h 1 ms interval timer 14 0038h programmable interval timer 15 003ch reserved 16 0040h reserved 17 0044h 16-bit free running timer wrap 18 0048h int2 19 004ch reserved 20 0050h gpio port 2 21 0054h reserved 22 0058h reserved 23 005ch reserved 24 0060h reserved 25 0064h sleep timer table 70. interrupt numbers, priorities, vectors (continued) interrupt priority interrupt address name interrupt source (timer, gpio, etc.) interrupt tak en or posted interrupt pending interrupt gie interrupt vector mask bit setting d r q 1 priority encoder m8c c o r e interrupt request ... int_mskx int_clrx write cpu_f[0] ...
cyrf69213 document number: 001-07552 rev. *g page 52 of 85 interrupt processing the sequence of events that occur during interrupt processing is as follows: an interrupt becomes active, either because: a. the interrupt condition occurs (for example, a timer expires). b. a previously posted interrupt is enabled through an update of an interrupt mask register. c. an interrupt is pending and gie is set from 0 to 1 in the cpu flag register. d. the gpio interrupts are edge triggered. the current executing instruction finishes. the internal interrupt is dispatched, taking 13 cycles. during this time, the following actions occur: a. the msb and lsb of program counter and flag registers (cpu_pc and cpu_f) are stored onto the program stack by an automatic call instruction (13 cycles) generated during the interrupt acknowledge process. b. the pch, pcl, and flag register (cpu_f) are stored onto the program stack (in that order) by an automatic call instruction (13 cycles) gen erated during the interrupt acknowledge process. c. the cpu_f register is then cleared. because this clears the gie bit to 0, additional interrupts are temporarily disabled d. the pch (pc[15:8]) is cleared to zero. e. the interrupt vector is read from the interrupt controller and its value placed into pcl (pc[7:0]). this sets the program counter to point to the appropriate address in the interrupt table (for example, 0004h for the por/lvd interrupt). program execution vectors to the interrupt table. typically, a ljmp instruction in the interrupt table sends execution to the user's interrupt service routine (isr) for this interrupt. the isr executes. note that interrupts are disabled because gie = 0. in the isr, interrupts can be re-enabled if desired by setting gie = 1 (care must be taken to avoid stack overflow). the isr ends with a reti instruction which restores the program counter and flag registers (cpu_pc and cpu_f). the restored flag register re-enables interrupts, because gie = 1 again. execution resumes at the next instruction, after the one that occurred before the interrupt. however, if there are more pending interrupts, the subsequent interrupts are processed before the next normal program instruction. interrupt latency the time between the assertion of an enabled interrupt and the start of its isr can be calculated from the following equation. latency = time for curr ent instruction to fini sh + time for internal interrupt routine to execute + time for ljmp instruction in interrupt table to execute. for example, if the 5 cycle jmp instruction is executing when an interrupt becomes active, the total number of cpu clock cycles before the isr begins would be as follows: (1 to 5 cycles for jmp to finish) + (13 cycles for interrupt routine) + (7 cycles for ljmp) = 21 to 25 cycles. in the example above, at 24 mhz, 25 clock cycles take 1.042 ? s. interrupt registers the interrupt registers are discussed it the following sections. interrupt clear register the interrupt clear registers (int_clrx) are used to enable the individual interrupt sources? ability to clear posted interrupts. when an int_clrx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. therefore, reading these registers gives the user the ability to determine all posted interrupts. table 71. interrupt clear 0 (int_clr0) [0xda] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits clears the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the ens wint (bit 7 of the int_msk3 register) posts the corresponding hardware interrupt
cyrf69213 document number: 001-07552 rev. *g page 53 of 85 interrupt mask registers the interrupt mask registers (int_mskx) are used to enable the individual interrupt sources? ability to create pending inter- rupts. there are four interrupt mask registers (int_msk0, int_msk1, int_msk2, and int_ msk3), which may be referred to in general as int_mskx. if cleared, each bit in an int_mskx register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). however, an interrupt can still post even if its mask bit is zero. all int_mskx bits are independent of all other int_mskx bits. if an int_mskx bit is set, the interrupt source associated with that mask bit may generate an interrupt that becomes a pending interrupt. the enable software interrupt (enswint) bit in int_msk3[7] determines the way an individual bit value written to an int_clrx register is interpreted. when is cleared, writing 1's to an int_clrx register has no effect. however, writing 0's to an int_clrx register, when enswint is cleared, causes the corresponding interrupt to clear. if the enswint bit is set, any 0?s written to the int_clrx registers are ignored. however, 1?s written to an int_clrx register, while enswint is set, causes an interrupt to post for the corresponding interrupt. software interrupts can aid in debugging interrupt service routines by eliminating th e need to create system level interactions that are someti mes necessary to create a hardware-only interrupt. table 72. interrupt clear 1 (int_clr1) [0xdb] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer 1 ms timer usb active usb reset usb ep2 usb ep1 usb ep0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits clears the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the ens wint (bit 7 of the int_msk3 register) posts the corresponding hardware interrupt bit 7 reserved table 73. interrupt clear 2 (int_clr2) [0xdc] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved reserved reserved gpio port 2 reserved int2 16-bit counter wrap reserved read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits clears the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the ens wint (bit 7 of the int_msk3 register) posts the corresponding hardware interrupt bits 7,6,5,3,0reserved table 74. interrupt mask 3 (int_msk3) [0xde] [r/w] bit # 7 6 5 4 3 2 1 0 field enswint reserved read/write r/w ? ? ? ? ? ? ? default 0 0 0 0 00 0 0 bit 7 enable software interrupt (enswint) 0 = disable. writing 0?s to an int_clrx register, when enswin t is cleared, causes the corresponding interrupt to clear 1 = enable. writing 1?s to an int_clrx register, when enswint is set, causes the corresponding interrupt to post bits 6:0 reserved
cyrf69213 document number: 001-07552 rev. *g page 54 of 85 table 75. interrupt mask 2 (int_msk2) [0xdf] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved reserved reserved gpio port 2 int enable reserved int2 int enable 16-bit counter wrap int enable reserved read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 reserved bit 6 reserved bit 5 reserved bit 4 gpio port 2 interrupt enable 0 = mask gpio port 2 interrupt 1 = unmask gpio port 2 interrupt bit 3 reserved bit 2 int2 interrupt enable 0 = mask int2 interrupt 1 = unmask int2 interrupt bit 1 16-bit counter wrap interrupt enable 0 = mask 16-bit counter wrap interrupt 1 = unmask 16-bit counter wrap interrupt bit 0 reserved table 76. interrupt mask 1 (int_msk1) [0xe1] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer int enable 1 ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 reserved bit 6 prog interval timer interrupt enable 0 = mask prog interval timer interrupt 1 = unmask prog interval timer interrupt bit 5 1 ms timer interrupt enable 0 = mask 1 ms interrupt 1 = unmask 1 ms interrupt bit 4 usb active interrupt enable 0 = mask usb active interrupt 1 = unmask usb active interrupt bit 3 usb reset interrupt enable 0 = mask usb reset interrupt 1 = unmask usb reset interrupt bit 2 usb ep2 interrupt enable 0 = mask ep2 interrupt 1 = unmask ep2 interrupt bit 1 usb ep1 interrupt enable 0 = mask ep1 interrupt 1 = unmask ep1 interrupt bit 0 usb ep0 interrupt enable 0 = mask ep0 interrupt 1 = unmask ep0 interrupt
cyrf69213 document number: 001-07552 rev. *g page 55 of 85 interrupt vector clear register table 77. interrupt mask 0 (int_msk0) [0xe0] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 gpio port 1 interrupt enable 0 = mask gpio port 1 interrupt 1 = unmask gpio port 1 interrupt bit 6 sleep timer interrupt enable 0 = mask sleep timer interrupt 1 = unmask sleep timer interrupt bit 5 int1 interrupt enable 0 = mask int1 interrupt 1 = unmask int1 interrupt bit 4 gpio port 0 interrupt enable 0 = mask gpio port 0 interrupt 1 = unmask gpio port 0 interrupt bit 3 spi receive interrupt enable 0 = mask spi receive interrupt 1 = unmask spi receive interrupt bit 2 spi transmit interrupt enable 0 = mask spi transmit interrupt 1 = unmask spi transmit interrupt bit 1 int0 interrupt enable 0 = mask int0 interrupt 1 = unmask int0 interrupt bit 0 por/lvd interrupt enable 0 = mask por/lvd interrupt 1 = unmask por/lvd interrupt table 78. interrupt vector clear register (int_vc) [0xe2] [r/w] bit # 7 6 5 4 3 2 1 0 field pending interrupt [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 the interrupt vector clear register (int_vc) holds the interrupt vector for the highest priority pending interrupt when read, a nd when written clears all pending interrupts bits 7:0 pending interrupt [7:0] 8-bit data value holds the interrupt vector for the highest priority pending interrupt. writing to this register clears all pen ding in- terrupts
cyrf69213 document number: 001-07552 rev. *g page 56 of 85 usb transceiver usb transceiver configuration vreg control table 79. usb transceiver configure register (usbxcr) [0x74] [r/w] bit # 7 6 5 4 3 2 1 0 field usb pull up enable reserved usb force state read/write r/w ? ? ? ? ? ? r/w default 0 0 0 0 00 0 0 bit 7 usb pull up enable 0 = disable the pull up resistor on d? 1 = enable the pull up resistor on d?. this pull up is to v cc if vreg is not enabled or to the internally generated 3.3 v when vreg is enabled. this bit should be cleared in sleep mode. bits 6:1 reserved bit 0 usb force state this bit allows the state of the usb i/o pins dp and d+ to be forced to a state while usb is enabled 0 = disable usb force state 1 = enable usb force state. allows the d? and d+ pins to be controlled by p1.1 and p1.0 respectively when the usbio is in usb mode. refer to ta b l e 4 8 for more information note the usb transceiver has a dedicated 3.3 v regulator for usb si gnalling purposes and to provide for the 1.5k d? pull up. unlike the other 3.3 v regulator, this regulator cannot be contro lled/accessed by firmware. when the device is suspended, this regulator is disabled along with the bandgap (which provides t he reference voltage to the regulator) and the d? line is pulled up to 5 v through an alternate 6.5k resistor. during wakeup following a suspend, the band gap and the regulator are switched on in an y order. under an extremely rare case when the device wakes up following a bus reset condition and the voltage regulator and the band gap turn on in that particular order, there is possibility of a glitch/low pulse occurring on the d? line. the host can mi sinterpret this as a deattach condition. this condition, although rare, can be avoided by keeping the bandgap circuitry enabled during sle ep. this is achieved by setting the ?no buzz? bit, bit[5] in the osc_ cr0 register. this is an issue only if the device is put to sl eep during a bus reset condition table 80. vreg control register (vregcr) [0x73] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved keep alive vreg enable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 00 0 0 bits 7:2 reserved bit 1 keep alive keep alive when set allows the voltage regulator to source up to 20 a of current when voltage regulator is disabled, p12cr[0],p12cr[7] should be cleared. 0 = disabled 1 = enabled bit 0 vreg enable this bit turns on the 3.3 v voltage regulator. the voltage regulator only functions within specifications when v cc is above 4.35 v. this block should not be enabled when v cc is below 4.35 v ? although no damage or irregularities occurs if it is enabled below 4.35 v 0 = disable the 3.3 v voltage regulator output on the vreg/p1.2 pin 1 = enable the 3.3 v voltage regulator output on the vreg/p1.2 pin. gpio functionality of p1.2 is disabled note use of the alternate drive on pins p1.3?p1.6 requires that the vreg enable bit be set to enable the regulator and provide the alternate voltage
cyrf69213 document number: 001-07552 rev. *g page 57 of 85 usb serial interface engine (sie) the sie allows the microcontroller to communicate with the usb host at low speed data rates (1.5 mbps). the sie simplifies the interface between the microcontroller and usb by incorporating hardware that handles the following usb bus activity independently of the microcontroller: translating the encoded received data and formatting the data to be transmitted on the bus crc checking and generation. flagging the microcontroller if errors exist during transmission address checking. ignoring the transactions not addressed to the device sending appropriate ack/nak/stall handshakes identifying token type (setup, in, or out). setting the appro- priate token bit after a valid token is received placing valid received data in the appropriate endpoint fifos sending and updating the data toggle bit (data1/0) bit stuffing/unstuffing. firmware is required to handle the rest of the usb interface with the following tasks: coordinate enumeration by decoding usb device requests fill and empty the fifos suspend/resume coordination verify and select data toggle values usb device table 81. usb device addr ess (usbcr) [0x40] [r/w] bit # 7 6 5 4 3 2 1 0 field usb enable device address[6:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 t he content of this register is cleared when a usb bus reset condition occurs bit 7 usb enable this bit must be enabled by firmware before the serial interface engine (sie) responds to usb traffic at the address specified in device address [6:0]. when this bit is cleared, the usb transceiver enters power down state. user?s firm- ware should clear this bit prior to entering sleep mode to save power 0 = disable usb device address and put the usb transceiver into power down state 1 = enable usb device address and put the usb transceiver into normal operating mode bits 6:0 device address [6:0] these bits must be set by firmware during the usb enume ration process (for example, setaddress) to the non-zero address assigned by the usb host
cyrf69213 document number: 001-07552 rev. *g page 58 of 85 table 82. endpoint 0, 1, and 2 count (ep0cnt?ep2cnt) [0x41, 0x43, 0x45] [r/w] bit # 7 6 5 4 3 2 1 0 field data toggle data valid reserved byte count[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 data toggle this bit selects the data packet's toggle state. for in transac tions, firmware must set this bit to the select the trans- mitted data toggle. for out or setup transactions, the hardware sets this bit to the state of the received data tog- gle bit. 0 = data0 1 = data1 bit 6 data valid this bit is used for out and setup tokens only. this bit is cleared to ?0? if crc, bitstuff, or pid errors have occurred. this bit does not update for some endpoint mode settings 0 = data is invalid. if enabled, the endpoint interrupt occurs even if invalid data is received 1 = data is valid bits 5:4 reserved bits 3:0 byte count bit [3:0] byte count bits indicate the number of data bytes in a transac tion: for in transactions, firmwa re loads the count with the number of bytes to be transmitted to the host from the endpo int fifo. valid values are 0 to 8 inclusive. for out or setup transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the crc bytes. valid values are 2?10 inclusive. for endpoint 0 count register, whenever the count updates from a setup or out transaction, the count register locks and cannot be written by the cpu. reading the register unlocks it. this prevents firmware from overwriting a status update on it
cyrf69213 document number: 001-07552 rev. *g page 59 of 85 endpoint 0 mode because both firmware and the sie are allowed to write to the endpoint 0 mode and count registers the sie provides an interlock ing mechanism to prevent accidental overwriting of data. when the sie writes to these registers they are locked and the pr ocessor cannot write to them until after it has read them. wri ting to this register clears the upper four bits regardless of the value written. table 83. endpoint 0 mode (ep0mode) [0x44] [r/w] bit # 7 6 5 4 3 2 1 0 field setup received in received out received ack?d trans mode[3:0] read/write r/c[3] r/c[3] r/c[3] r/c[3] r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 setup received this bit is set by hardware when a valid setup packet is received. it is forced high from the start of the data packet phase of the setup transactions until the end of the data phase of a control write transfer and cannot be cleared dur- ing this interval. while this bit is set to ?1?, the cpu cann ot write to the ep0 fifo. this prevents firmware from over- writing an incoming setup transaction before firmware has a chance to read the setup data this bit is cleared by any non-locked writes to the register 0 = no setup received 1 = setup received bit 6 in received this bit, when set, indicates a valid in packet has been received. this bit is updated to ?1? after the host acknowl- edges an in data packet.when clear, it indicates that either no in has been received or that the host didn?t acknowl- edge the in data by sending an ack handshake this bit is cleared by any non-locked writes to the register. 0 = no in received 1 = in received bit 5 out received this bit, when set, indicates a valid out packet has been received and acked. this bit is updated to ?1? after the last received packet in an out transaction. when clear, it indicates no out received this bit is cleared by any non-locked writes to the register 0 = no out received 1 = out received bit 4 ack?d transaction the ack?d transaction bit is set whenever the sie engages in a transaction to the register?s endpoint that completes with a ack packet this bit is cleared by any non-locked writes to the register 1 = the transaction completes with an ack 0 = the transaction does not complete with an ack bits 3:0 mode [3:0] the endpoint modes determine how the sie responds to usb traffic that the host sends to the endpoint. the mode controls how the usb sie responds to traffic and how the usb sie changes the mode of that endpoint as a result of host packets to the endpoint
cyrf69213 document number: 001-07552 rev. *g page 60 of 85 endpoint data buffers the three data buffers are used to hold data for both in and out transactions. each data buffer is 8 bytes long. the reset valu es of the endpoint data registers are unknown. unlike past encore parts the usb data buffers are only accessible in the i/o space of the processor. table 84. endpoint 1 and 2 mode (ep1mode ? ep2mode) [0x45, 0x46] [r/w] bit # 7 6 5 4 3 2 1 0 field stall reserved nak int enable ack?d transaction mode[3:0] read/write r/w r/w r/w r/c (note 3) r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 stall when this bit is set the sie stalls an out packet if the mode bits are set to ack-out, and the sie stalls an in packet if the mode bits are set to ack-in. this bit must be clear for all other modes bit 6 reserved bit 5 nak int enable this bit, when set, causes an endpoint interrupt to be generated even when a transfer completes with a nak. unlike encore, cyrf69213 family members do not generate an endpoint interrupt under these conditions unless this bit is set 0 = disable interrupt on nak?d transactions 1 = enable interrupt on nak?d transaction bit 4 ack?d transaction the ack?d transaction bit is set whenever the sie engages in a transaction to the register?s endpoint that completes with an ack packet this bit is cleared by any writes to the register 0 = the transaction does not complete with an ack 1 = the transaction completes with an ack bits 3:0 mode [3:0] the endpoint modes determine how the sie responds to usb traffic that the host sends to the endpoint. the mode controls how the usb sie responds to traffic and how the usb sie changes the mode of that endpoint as a result of host packets to the endpoint. note when the sie writes to the ep1mode or t he ep2mode register it blocks firmware writes to the ep2mo de or the ep1mode registers, respectively (if both writes o ccur in the same clock cycle). this is because the design employs only one common ?upd ate? signal for both ep1mode and ep2mode registers. thus, when sie writes to the ep1mode register, the update signal is set and this prevents firmware writes to ep2mode register. sie writes to the endpoint mode registers have higher priority than firmware writes. this mode register write block situation can put the en dpoints in incorrect modes. firm ware must read the ep1/2mode registers immediately following a firmware writ e and rewrite if the value read is incorrect table 85. endpoint 0 data (ep0data) [0x50-0x57] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 0 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57
cyrf69213 document number: 001-07552 rev. *g page 61 of 85 table 86. endpoint 1 data (ep1data) [0x58-0x5f] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 1 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5f table 87. endpoint 2 data (ep2data) [0x60-0x67] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 2 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67
cyrf69213 document number: 001-07552 rev. *g page 62 of 85 usb mode tables mode column the 'mode' column contains the mnemonic names given to the modes of the endpoint. the mode of the endpoint is determined by the four-bit binaries in the 'encoding' column as discussed in the following section. the status in and status out represent the status in or out stage of the control transfer. encoding column the contents of the 'encoding' column represent the mode bits [3:0] of the endpoint mode registers ( table 83 on page 59 and table 84 on page 60 ). the endpoint modes determine how the sie responds to different tokens that the host sends to the endpoints. for example, if the mode bits [3:0] of the endpoint 0 mode register are set to '0001', which is nak in/out mode, the sie sends an ack handshake in response to setup tokens and nak any in or out tokens. setup, in, and out columns depending on the mode specified in the 'encoding' column, the 'setup', 'in', and 'out' columns contain the sie's responses when the endpoint receives setup, in, and out tokens, respectively. a 'check' in the out column means that upon receiving an out token the sie checks to see whet her the out is of zero length and has a data toggle (data1/0) of 1. if these conditions are true, the sie responds with an ack. if any of the above conditions is not met, the sie responds with either a stall or ignore. a 'tx count' entry in the in column means that the sie transmits the number of bytes specified in the byte count bit [3:0] of the endpoint count register ( table 82 on page 58 ) in response to any in token. mode encoding setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint. used by data and control endpoints nak in/out 0001 accept nak nak nak in and out token. control endpoint only status out only 0010 accept stall check stall in and ack zero byte out. control endpoint only stall in/out 0011 accept stall stall stall in and out token. control endpoint only status in only 0110 accept tx0 byte stall stall out and send zero byte data for in token. control endpoint only ack out ? status in 1011 accept tx0 byte ack ack the out token or send zero byte data for in token. control endpoint only ack in ? status out 1111 accept tx count check respond to in data or status out. control endpoint only nak out 1000 ignore ignore nak send nak handshake to out token. data endpoint only ack out (stall = 0) 1001 ignore ignore ack this mode is changed by the sie to mode 1000 on issuance of ack handshake to an out. data endpoint only ack out (stall = 1) 1001 ignore ignore stall stall the out transfer nak in 1100 ignore nak ignore send nak handshake for in token. data endpoint only ack in (stall = 0) 1101 ignore tx count ignore this mode is changed by the sie to mode 1100 after receiving ack handshake to an in data. data endpoint only ack in (stall = 1) 1101 ignore stall ignore stall the in transfer. data endpoint only reserved 0101 ignore ignore ignore these modes are not supported by sie. firmware should not use this mode in control and data endpoints reserved 0111 ignore ignore ignore reserved 1010 ignore ignore ignore reserved 0100 ignore ignore ignore reserved 1110 ignore ignore ignore
cyrf69213 document number: 001-07552 rev. *g page 63 of 85 details of mode for di ffering traffic conditions sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo control endpoint disabled 0000 x x x x ignore all stall_in_out 0011 setup > 10 x x junk ignore 0011 setup < 10 invalid x junk ignore 0011 setup < 10 valid x ack 1 1 0001 update 1 update data yes ack setup 0011 in x x x stall stall in 0011 out > 10 x x ignore 0011 out < 10 invalid x ignore 0011 out < 10 valid x stall stall out nak_in_out 0001 setup > 10 x x junk ignore 0001 setup < 10 invalid x junk ignore 0001 setup < 10 valid x ack 1 1 0001 update 1 update data yes ack setup 0001 in x x x nak nak in 0001 out >10 x x ignore 0001 out < 10 invalid x ignore 0001 out < 10 valid x nak nak out ack_in_status_out 1111 setup > 10 x x junk ignore 1111 setup < 10 invalid x junk ignore 1111 setup < 10 valid x ack 1 1 0001 update 1 update data yes ack setup 1111 in x x x tx host not ack'd 1111 in x x x tx 1 1 0001 yes host ack'd 1111 out > 10 x x ignore 1111 out < 10 invalid x ignore 1111 out < 10, <>2 valid x stall 0011 yes bad status 1111 out 2 valid 0 stall 0011 yes bad status 1111 out 2 valid 1 ack 1 1 0010 1 1 2 yes good status status_out 0010 setup >10 x x junk ignore 0010 setup < 10 invalid x junk ignore 0010 setup < 10 valid x ack 1 1 0001 update 1 update data yes ack setup 0010 in x x x stall 0011 yes stall in 0010 out >10 x x ignore 0010 out < 10 invalid x ignore 0010 out < 10, <>2 valid x stall 0011 yes bad status
cyrf69213 document number: 001-07552 rev. *g page 64 of 85 0010 out 2 valid 0 stall 0011 yes bad status 0010 out 2 valid 1 ack 1 1 1 1 2 yes good status ack_out_status_in 1011 setup >10 x x junk ignore 1011 setup < 10 invalid x junk ignore 1011 setup < 10 valid x ack 1 1 0001 update 1 update data yes ack setup 1011 in x x x tx 0 host not ack'd 1011 in x x x tx 0 1 1 0011 yes host ack'd 1011 out >10 x x junk ignore 1011 out < 10 invalid x junk ignore 1011 out < 10 valid x ack 1 1 0001 update 1 update data yes good out status_in 0110 setup >10 x x junk ignore 0110 setup < 10 invalid x junk ignore 0110 setup < 10 valid x ack 1 1 0001 update 1 update data yes ack setup 0110 in x x x tx 0 host not ack'd 0110 in x x x tx 0 1 1 0011 yes host ack'd 0110 out >10 x x ignore 0110 out < 10 invalid x ignore 0110 out < 10 valid x stall 0011 yes stall out data out endpoints ack out (stall bit = 0) 1001 in x x x ignore 1001 out > max x x junk ignore 1001 out < max invalid invalid junk ignore 1001 out < max valid valid ack 1 1000 update 1 update data yes ack out ack out (stall bit = 1) 1001 in x x x ignore 1001 out > max x x ignore 1001 out < max invalid invalid ignore 1001 out < max valid valid stall stall out nak out 1000 in x x x ignore 1000 out > max x x ignore 1000 out < max invalid invalid ignore 1000 out < max valid valid nak if enabled nak out details of mode for di ffering traffic conditions (continued) sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo
cyrf69213 document number: 001-07552 rev. *g page 65 of 85 data in endpoints ack in (stall bit = 0) 1101 out x x x ignore 1101 in x x x host not ack'd 1101 in x x x tx 1 1100 yes host ack'd ack in (stall bit = 1) 1101 out x x x ignore 1101 in x x x stall stall in nak in 1100 out x x x ignore 1100 in x x x nak if enabled nak in details of mode for di ffering traffic conditions (continued) sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo
cyrf69213 document number: 001-07552 rev. *g page 66 of 85 register summary addr name 7 6 5 4 3 2 1 0 r/w default 00 p0data p0.7 reserved reserved p0.4 / int2 p0.3 / int1 reserved p0.1 reserved b--bbb-- 00000000 01 p1data p1.7 p1.6/smi so p1.5/sm osi p1.4 / sclk p1.3 / ssel p1.2 / vreg p1.1/d? p1.0/d+ bbbbbbbb 00000000 02 p2data res p2.1?p2.0 bbbbbbbb 00000000 06 p01cr reserved int enable int act low ttl thresh high sink open drain pull up enable output enable --bbbbbb 00000000 08?09 p03cr? p04cr reserved reserved int act low ttl thresh reserved open drain pull up enable output enable --bbbbbb 00000000 0c p07cr reserved int enable int act low ttl thresh reserved open drain pull up enable output enable -bbbbbbb 00000000 0d p10cr reserved int enable int act low reserved 5k pull up enable output enable -bb----b 00000000 0e p11cr reserved int enable int act low reserved open drain reserved output enable -bb--b-b 00000000 0f p12cr clk output int enable int act low ttl thresh reserved open drain pull up enable output enable bbbbbbbb 00000000 10 p13cr reserved int enable int act low 3.3 v drive high sink open drain pull up enable output enable -bbbbbbb 00000000 11?13 p14cr? p16cr spi use int enable int act low 3.3 v drive high sink open drain pull up enable output enable bbbbbbbb 00000000 14 p17cr reserved int enable int act low ttl thresh high sink open drain pull up enable output enable -bbbbbbb 00000000 15 p2cr reserved int enable int act low ttl thresh reserved open drain pull up enable output enable -bbbbbbb 00000000 20 frtmrl free-running timer [7:0] bbbbbbbb 00000000 21 frtmrh free-running timer [15:8] bbbbbbbb 00000000 26 pitmrl prog interval timer [7:0] bbbbbbbb 00000000 27 pitmrh reserved prog interval timer [11:8] ----bbbb 00000000 28 pirl prog interval [7:0] bbbbbbbb 00000000 29 pirh reserved prog interval [11:8] ----bbbb 00000000 30 cpuclkc r reserved -------- 00010000 31 itmrclkc r tcapclk divider tcapclk select itmrclk divider itmrclk select bbbbbbbb 10001111 32 clkiocr reserved reserved clkout select ---bbbbb 00000000 34 iosctr foffset[2:0] gain[4:0] bbbbbbbb 000ddddd 35 xosctr reserved reserved reserved mode ---bbb-b 000ddd0d 36 lposctr 32 khz low power reserved 32 khz bias trim [1:0] 32 khz freq trim [3:0] b-bbbbbb dddddddd 39 osclckc r reserved fine tune only usb osclock disable ------bb 00000000 3c spidata spidata[7:0] bbbbbbbb 00000000 3d spicr swap lsb first comm mode cpol cpha sclk select bbbbbbbb 00000000 40 usbcr usb enable device address[6:0] bbbbbbbb 00000000
cyrf69213 document number: 001-07552 rev. *g page 67 of 85 41 ep0cnt data to g g l e data valid reserved byte count[3:0] bbbbbbbb 00000000 42 ep1cnt data to g g l e data valid reserved byte count[3:0] bbbbbbbb 00000000 43 ep2cnt data to g g l e data valid reserved byte count[3:0] bbbbbbbb 00000000 44 ep0mode setup rcv?d in rcv?d out rcv?d ack?d trans mode[3:0] ccccbbbb 00000000 45 ep1mode stall reserved nak int enable ack?d trans mode[3:0] b-bcbbbb 00000000 46 ep2mode stall reserved nak int enable ack?d trans mode[3:0] b-bcbbbb 00000000 50?57 ep0data endpoint 0 data buffer [7:0] bbbbbbbb ???????? 58?5f ep1data endpoint 1 data buffer [7:0] bbbbbbbb ???????? 60?67 ep2data endpoint 2 data buffer [7:0] bbbbbbbb ???????? 73 vregcr reserved keep alive vreg enable ------bb 00000000 74 usbxcr usb pull up enable reserved usb force state b------b 00000000 da int_clr0 gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd bbbbbbbb 00000000 db int_clr1 reserved prog interval timer 1-ms timer usb active usb reset usb ep2 usb ep1 usb ep0 -bbbbbbb 00000000 dc int_clr2 reserved reserved reserved gpio port 2 reserved int2 16-bit counter wrap reserved -bbbbbb- 00000000 de int_msk3 enswint reserved b------- 00000000 df int_msk2 reserved reserved reserved gpio port 2 int enable reserved int2 int enable 16-bit counter wrap int enable reserved ---bbbb- 00000000 e0 int_msk0 gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable bbbbbbbb 00000000 e1 int_msk1 reserved prog interval timer int enable 1-ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable bbbbbbbb 00000000 e2 int_vc pending interrupt [7:0] bbbbbbbb 00000000 e3 reswdt reset watchdog timer [7:0] wwwwwww w 00000000 -- cpu_a temporary register t1 [7:0] -------- 00000000 -- cpu_x x[7:0] -------- 00000000 -- cpu_pcl program counter [7:0] -------- 00000000 -- cpu_pch program counter [15:8] -------- 00000000 -- cpu_sp stack pointer [7:0] -------- 00000000 -- cpu_f reserved xoi super carry zero global ie ---brwww 00000010 ff cpu_scr gies reserved wdrs pors sleep reserved reserved stop r-ccb--b 00010000 register summary (continued) addr name 7 6 5 4 3 2 1 0 r/w default
cyrf69213 document number: 001-07552 rev. *g page 68 of 85 legend in the r/w column, b = both read and write r = read only w = write only c = read/clear ? = unknown d = calibration value. should not change during normal use 1e0 osc_cr0 reserved no buzz sleep timer [1:0] cpu speed [2:0] --bbbbbb 00000000 1e3 lvdcr reserved porlev[1:0] reserved vm[2:0] --bb-bbbb 00000000 1e4 vltcmp reserved lvd ppor ------rr 00000000 1eb eco_tr sleep duty cycle [1:0] reserved bb------ 00000000 register summary (continued) addr name 7 6 5 4 3 2 1 0 r/w default
cyrf69213 document number: 001-07552 rev. *g page 69 of 85 radio function register descriptions all registers are read and writeable, except where noted. register s may be written to or read from either individually or in se quential groups. a single-byte read or write reads or writes from the addressed register. in crementing burst read and write is a sequenc e that begins with an address, and then reads or writes to/from each register in address order for as long as clocking continues. it i s possible to repeatedly read (poll) a single register using a non-increme nting burst read. these registers are managed and configured ove r spi by the user firmware running in the microcontroller function. table 88. register map summary address mnemonic b7 b6 b5 b4 b3 b2 b1 b0 default [4] access [4] 0x00 channel_adr not used channel -1001000 -bbbbbbb 0x01 tx_length_adr tx length 00000000 bbbbbbbb 0x02 tx_ctrl_adr tx go tx clr txb15 irqen txb8 irqen txb0 irqen txberr irqen txc irqen txe irqen 00000011 bbbbbbbb 0x03 tx_cfg_adr not used not used data code length data mode pa setting --000101 --bbbbbb 0x04 tx_irq_status_adr os irq lv irq txb15 irq txb8 irq txb0 irq txberr irq txc irq txe irq 10111000 rrrrrrrr 0x05 rx_ctrl_adr rx go rsvd rxb16 irqen rxb8 irqen rxb1 irqen rxberr irqen rxc irqen rxe irqen 00000111 bbbbbbbb 0x06 rx_cfg_adr agc en lna att hilo fast turn en not used rxow en vld en 10010-10 bbbbb-bb 0x07 rx_irq_status_adr rxow irq sofdet irq rxb16 irq rxb8 irq rxb1 irq rxberr irq rxc irq rxe irq 00000000 brrrrrrr 0x08 rx_status_adr rx ack pkt err eop err crc0 bad crc rx code rx data mode 00001--- rrrrrrrr 0x09 rx_count_adr rx count 00000000 rrrrrrrr 0x0a rx_length_adr rx length 00000000 rrrrrrrr 0x0b pwr_ctrl_adr pmu en lvirq en pmu mode force rsvd lvi th pmu outv 10100000 bbb-bbbb 0x0c xtal_ctrl_adr xout fn xsirq en not used not used freq 000--100 bbb--bbb 0x0d io_cfg_adr irq od irq pol miso od xout od pactl od pactl gpio spi 3pin irq gpio 00000000 bbbbbbbb 0x0e gpio_ctrl_adr xout op miso op pactl op irq op xout ip miso ip pactl ip irq ip 0000---- bbbbrrrr 0x0f xact_cfg_adr ack en not used frc end end state ack to 1-000000 b-bbbbbb 0x10 framing_cfg_adr sop en sop len len en sop th 10100101 bbbbbbbb 0x11 data32_thold_adr not used not used not used not used th32 ----0100 ----bbbb 0x12 data64_thold_adr not used not used not used th64 ---01010 ---bbbbb 0x13 rssi_adr sop not used lna rssi 0-100000 r-rrrrrr 0x14 eop_ctrl_adr hen hint eop 10100100 bbbbbbbb 0x15 crc_seed_lsb_adr crc seed lsb 00000000 bbbbbbbb 0x16 crc_seed_msb_adr crc seed msb 00000000 bbbbbbbb 0x17 tx_crc_lsb_adr crc lsb -------- rrrrrrrr 0x18 tx_crc_msb_adr crc msb -------- rrrrrrrr 0x19 rx_crc_lsb_adr crc lsb 11111111 rrrrrrrr 0x1a rx_crc_msb_adr crc msb 11111111 rrrrrrrr 0x1b tx_offset_lsb_adr strim lsb 00000000 bbbbbbbb 0x1c tx_offset_msb_adr not used not used not used not used strim msb ----0000 ----bbbb 0x1d mode_override_adr rsvd rsvd frc sen frc awake not used not used rst 00000--0 wwwww--w 0x1e rx_override_adr ack rx rxtx dly man rxack frc rxdr dis crc0 dis rxcrc ace not used 0000000- bbbbbbb- 0x1f tx_override_adr ack tx frc pre rsvd man txack ovrd ack dis txcrc rsvd tx inv 00000000 bbbbbbbb 0x27 clk_override_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwwww 0x28 clk_en_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwwww 0x29 rx_abort_adr rsvd rsvd abort en rsvd rsvd rsvd rsvd rsvd 00000000 wwwwwwww 0x32 auto_cal_time_adr auto_cal_time_max 00000011 wwwwwwww 0x35 auto_cal_offset_adr auto_cal_offset_minus_4 00000000 wwwwwwww 0x39 analog_ctrl_adr rsvd rsvd rsvd rsvd rsvd rsvd rsvd all slow 00000000 wwwwwwww register files 0x20 tx_buffer_adr tx buffer file -------- wwwwwwww 0x21 rx_buffer_adr rx buffer file -------- rrrrrrrr 0x22 sop_code_adr sop code file note 5 bbbbbbbb 0x23 data_code_adr data code file note 6 bbbbbbbb 0x24 preamble_adr preamble file note 7 bbbbbbbb 0x25 mfg_id_adr mfg id file na rrrrrrrr notes 4. b = read/write; r = read only; w = write only; ?-? = not used, default value is undefined. 5. sop_code_adr default = 0x17ff9e213690c782. 6. data_code_adr default = 0x02f9939702fa5ce3012bf1db0132be6f. 7. preamble_adr default = 0x333302;the count value should be great than 4 for ddr and greater than 8 for sdr.
cyrf69213 document number: 001-07552 rev. *g page 70 of 85 absolute maximum ratings storage temperature ................................. ?40 c to +90 c ambient temperature with power applied ..... 0 c to +70 c supply voltage on any power supply pin relative to v ss ........................................?0.3 v to +3.9 v dc voltage to logic inputs [8] .............. ?0.3 v to v io + 0.3 v dc voltage applied to outputs in high z state ..................................... ?0.3 v to v io + 0.3 v static discharge voltage (digital) [9] ........................ >2000 v static discharge voltage (rf) [9] ............................... 1100 v latch up current .....................................+200 ma, ?200 ma ground voltage ................................................................ 0 v f osc (crystal frequency) .......................... 12 mhz 30 ppm dc characteristics (t = 25 ?? c) parameter description conditions min. typ. max. unit radio function operating voltages (for rf activity, v cc = v bat = 3.0 v to 3.6 v) v bat battery voltage 0 ?? c?70 ? c 2.4?3.6v v io v io voltage 1.8 ? 3.6 v v cc v cc voltage 0 ? c?70 ? c 2.4?3.6v mcu function operating voltages v dd_micro1 operating voltage no usb activity, cpu speed < 12 mhz 4.0 ? 5.25 v v dd_micro2 operating voltage usb activity, cpu speed < 12 mhz. flash programming 4.35 ? 5.25 v v lvd low voltage detect trip voltage (8 programmable trip points) 2.68 ? 4.87 v device current (for total current consumption in different mo des, for example radio, active , mcu, sleep, etc., add radio function current and mcu function current) i dd (gfsk) [10] average i dd , 1 mbps, slow channel pa = 5, 2-way, 4 bytes/10 ms ? 10.87 ? ma i dd (32-8dr) [10] average i dd , 250 kbps, fast channel pa = 5, 2-way, 4 bytes/10 ms ? 11.2 ? ma i sb sleep mode i dd radio function and mcu function in sleep mode, v reg in keep alive. ? 40.1 ? a radio function current (v dd_micro = 5.0 v, v reg enabled, mcu sleep) idle i cc radio off, xtal active xout disabled ? 2.1 ? ma i synth i cc during synth start ? 9.8 ? ma tx i cc i cc during transmit pa = 5 (?5 dbm) ? 22.4 ? ma tx i cc i cc during transmit pa = 6 (0 dbm) ? 27.7 ? ma tx i cc i cc during transmit pa = 7 (+4 dbm) ? 36.6 ? ma rx i cc i cc during receive lna off, att on ? 20.2 ? ma rx i cc i cc during receive lna on, att off ? 23.4 ? ma notes 8. it is permissible to connect voltages above v io to inputs through a series resistor limiting i nput current to 1 ma. ac timing not guaranteed. 9. human body model (hbm). 10. includes current drawn while starting crystal, starting syn thesizer, transmitting packet (including sop and crc16), changing to receive mode, and receiving ack handshake. device is in sleep except during this transaction.
cyrf69213 document number: 001-07552 rev. *g page 71 of 85 mcu function current (v dd_micro = 5.0 v, v reg disabled) i dd_micro1 v dd_micro operating supply current no gpio loading, 6 mhz ? 10 ? ma i sb1 standby current internal oscillators, bandgap, flash, cpu clock, timer clock, usb clock all disabled ? 4 10 a usb interface v on static output high 15k 5% ohm to v ss 2.8?3.6v v off static output low r up is enabled ? ? 0.3 v v di differential input sensitivity 0.2 ? ? v v cm differential input common mode range 0.8?2.5v v se single ended receiver threshold 0.8 ? 2 v c in transceiver capacitance ? ? 20 pf i io hi-z state data line leakage 0 v < v in < 3.3 v ?10 ? 10 a radio function gpio interface v oh1 output high voltage condition 1 at i oh = ?100.0 a v io ? 0.1 v io ?v v oh2 output high voltage condition 2 at i oh = ?2.0 ma v io ? 0.4 v io ?v v ol output low voltage at i ol = 2.0 ma ? 0 0.4 v v ih input high voltage 0.76 v io ?v io v v il input low voltage 0 ? 0.24 v io v i il input leakage current 0 < v in < v io ?1 0.26 +1 a c in pin input capacitance except xtal, rf n , rf p , rf bias ? 3.5 10 pf mcu function gpio interface r up pull up resistance 4 ? 12 k ? v icr input threshold voltage low, cmos mode low to high edge 40% ? 65% v cc v icf input threshold voltage low, cmos mode high to low edge 30% ? 55% v cc v hc input hysteresis voltage, cmos mode high to low edge 3% ? 10% v cc v ilttl input low voltage, ttl mode io-pin supply = 2.9?3.6 v ? ? 0.8 v v ihttl input high voltage, ttl mode io-pin supply = 4.0?5.5 v 2.0 ? ? v v ol1 output low voltage, high drive [11] i ol1 = 50 ma ? ? 0.8 v v ol2 output low voltage, high drive [11] i ol1 = 25 ma ? ? 0.4 v v ol3 output low voltage, low drive [11] i ol2 = 8 ma ? ? 0.4 v v oh output high voltage [11] i oh = 2 ma v cc ? 0.5 ? ? v dc characteristics (continued) (t = 25 ?? c) parameter description conditions min. typ. max. unit note 11. except for pins p1.0, p1.1 in gpio mode.
cyrf69213 document number: 001-07552 rev. *g page 72 of 85 3.3 v regulator i vreg max regulator output current v cc > 4.35 v ? ? 125 ma i ka keep alive current when regulator is disabled with ?keep alive? enable ? ? 20 a v reg1 v reg output voltage v cc > 4.35 v, 0 < temp < 40 c, 25 ma < i vreg < 125 ma 3.0?3.6v v reg2 v reg output voltage v cc > 4.35 v, 0 < temp < 40 c, 1 ma < i vreg < 25 ma 3.15 ? 3.45 v v ka keep alive voltage keep alive bit set in vregcr 2.35 ? 3.9 v dc characteristics (continued) (t = 25 ?? c) parameter description conditions min. typ. max. unit
cyrf69213 document number: 001-07552 rev. *g page 73 of 85 rf characteristics table 89. radio parameters parameter description conditions min. typ. max. unit rf frequency range subject to regulations. 2.400 ? 2.497 ghz receiver (t = 25 c, v cc = v bat = 3.0 v, f osc = 12.000 mhz, ber < 10 ?3 ) sensitivity 125 kbps 64-8dr ber 1e-3 ? ?97 ? dbm sensitivity 250 kbps 32-8dr ber 1e-3 ? ?93 ? dbm sensitivity cer 1e-3 ?80 ?87 ? dbm sensitivity gfsk ber 1e-3, all slow = 1 ? ?84 ? dbm lna gain ? 22.8 ? db att gain ??31.7? db maximum received signal lna on ?15 ?6 ? dbm rssi value for pwr in ?60 dbm [13] lna on ? 21 ? count rssi slope ? 1.9 ? db/count interference performance (cer 1e-3) co-channel interference rejection carrier-to-interf erence (c/i) c = ?60 dbm ? 9 ? db adjacent (1 mhz) channel selectivity c/i 1 mhz c = ?60 dbm ? 3 ? db adjacent (2 mhz) channel selectivity c/i 2 mhz c = ?60 dbm ? ?30 ? db adjacent (> 3 mhz) channel selectivity c/i > 3 mhz c = ?67 dbm ? ?38 ? db out-of-band blocking 30 mhz?12.75 mhz [12] c = ?67 dbm ? ?30 ? dbm intermodulation c = ?64 dbm, ? f = 5,10 mhz ? ?36 ? dbm receive spurious emission 800 mhz 100 khz resbw ? ?79 ? dbm 1.6 ghz 100 khz resbw ? ?71 ? dbm 3.2 ghz 100 khz resbw ? ?65 ? dbm transmitter (t = 25 c, v cc = v bat = 3.0 v, f osc = 12.000 mhz) maximum rf transmit power pa = 7 +2 4 +6 dbm maximum rf transmit power pa = 6 ?2 0 +2 dbm maximum rf transmit power pa = 5 ?7 ?5 ?3 dbm maximum rf transmit power pa = 0 ? ?35 ? dbm rf power control range ? 39 ? db rf power range control step size seven steps, monotonic ? 5.6 ? db frequency deviation min pn code pattern 10101010 ? 270 ? khz frequency deviation max pn code pattern 11110000 ? 323 ? khz error vector magnitude (fsk error) >0 dbm ? 10 ? %rms occupied bandwidth ?6 dbc, 100 khz resbw 500 876 ? khz notes 12. exceptions f/3 & 5c/3. 13. rssi value is not guaranteed. extensive variation from part to part.
cyrf69213 document number: 001-07552 rev. *g page 74 of 85 ac test loads and wavef orms for digital pins figure 19. ac test loads and waveforms for digital pins transmit spurious emission (pa = 7) in-band spurious second channel power (2 mhz) ? ?38 ? dbm in-band spurious third channel power (> 3 mhz) ? ?44 ? dbm non-harmonically related spurs (8.000 ghz) ? ?38 ? dbm non-harmonically related spurs (1.6 ghz) ? ?34 ? dbm non-harmonically related spurs (3.2 ghz) ? ?47 ? dbm harmonic spurs (second harmonic) ? ?43 ? dbm harmonic spurs (third harmonic) ? ?48 ? dbm fourth and greater harmonics ? ?59 ? dbm power management (crystal pn# ecera gf-1200008) crystal start to 10 ppm ? 0.7 1.3 ms crystal start to irq xsirq en = 1 ? 0.6 ? ms synth settle slow channels ? ? 270 s synth settle medium channels ? ? 180 s synth settle fast channels ? ? 100 s link turnaround time gfsk ? ? 30 s link turnaround time 250 kbps ? ? 62 s link turnaround time 125 kbps ? ? 94 s link turnaround time <125 kbps ? ? 31 s max. packet length < 60 ppm crystal-to-crystal all modes except 64-ddr and 64-sdr ? ? 40 bytes max. packet length < 60 ppm crystal-to-crystal 64-ddr and 64-sdr ? ? 16 bytes table 89. radio parameters (continued) parameter description conditions min. typ. max. unit 90% 10% v cc gnd 90% 10% all input pulses output 30 pf including jig and scope output r th equivalent to: v th thvenin equivalent rise time: 1 v/ns fall time: 1 v/ns output 5 pf including jig and scope max typical parameter unit r1 1071 ? r2 937 ? r th 500 ? v th 1.4 v v cc 3.00 v v cc output r1 r2 ac test loads dc test load
cyrf69213 document number: 001-07552 rev. *g page 75 of 85 ac electrical characteristics parameter description conditions min. typ. max. unit clock f imo internal main oscillator frequency no usb present 22.8 ? 25.2 mhz with usb present 23.64 ? 24.36 f ilo internal low power oscillator normal mode 29.44 ? 37.12 khz low power mode 35.84 ? 47.36 3.3 v regulator v orip output ripple voltage 45 ? 55 % usb driver t r1 transition rise time c load = 200 pf 75 ? ? ns t r2 transition rise time c load = 600 pf ? ? 300 ns t f1 transition fall time c load = 200 pf 75 ? ? ns t f2 transition fall time c load = 600 pf ? ? 300 ns t r rise/fall time matching 80 ? 125 % v crs output signal crossover voltage 1.3 ? 2.0 v usb data timing t drate low speed data rate ave. bit rate (1.5 mbps 1.5%) 1.4775 ? 1.5225 mbps t djr1 receiver data jitter tolerance to next transition ?75 ? 75 ns t djr2 receiver data jitter tolerance to pair transition ?45 ? 45 ns t deop differential to eop transition skew ?40 ? 100 ns t eopr1 eop width at receiver rejects as eop ? ? 330 ns t eopr2 eop width at receiver accept as eop 675 ? ? ns t eopt source eop width 1.25 ? 1.5 ? s t udj1 differential driver jitter to next transition ?95 ? 95 ns t udj2 differential driver jitter to pair transition ?95 ? 95 ns t lst width of se0 during diff. transition ??210ns non-usb mode driver characteristics t fps2 sdata/sck transition fall time 50 ? 300 ns spi timing t smck spi master clock rate f cpuclk /6 ??2mhz t ssck spi slave clock rate ? ? 2.2 mhz t sckh spi clock high time high for cpol = 0, low for cpol = 1 125 ? ? ns t sckl spi clock low time low for cpol = 0, high for cpol = 1 125 ? ? ns t mdo master data output time [14] sck to data valid ?25 ? 50 ns t mdo1 master data output time, first bit with cpha = 0 time before leading sck edge 100 ? ? ns note 14. in master mode first bit is available 0.5 spiclk cycle before master clock edge available on the sclk pin.
cyrf69213 document number: 001-07552 rev. *g page 76 of 85 figure 20. clock timing figure 21. usb data signal timing figure 22. clock timing t msu master input data setup time 50 ? ? ns t mhd master input data hold time 50 ? ? ns t ssu slave input data setup time 50 ? ? ns t shd slave input data hold time 50 ? ? ns t sdo slave data output time sck to data valid ? ? 100 ns t sdo1 slave data output time, first bit with cpha = 0 time after ss low to data valid ? ? 100 ns t sss slave select setup time before first sck edge 150 ? ? ns t ssh slave select hold time after last sck edge 150 ? ? ns ac electrical characteristics (continued) parameter description conditions min. typ. max. unit clock t cyc t cl t ch 90% 10% 90% 10% d ? d ? t r t f v crs v oh v ol clock t cyc t cl t ch
cyrf69213 document number: 001-07552 rev. *g page 77 of 85 figure 23. usb data signal timing figure 24. receiver jitter tolerance figure 25. differential to eop transition skew and eop width 90% 10% 90% 10% d ? d ? t r t f v crs v oh v ol differential data lines paired transitions n * t period + t jr2 t period consecutive transitions n * t period + t jr1 t jr t jr1 t jr2 t period differential data lines crossover point crossover point extended source eop width: t eopt receiver eop width: t eopr1 , t eopr2 diff. data to se0 skew n * t period + t deop
cyrf69213 document number: 001-07552 rev. *g page 78 of 85 figure 26. differential data jitter figure 27. spi master timing, cpha = 1 t period differential data lines crossover points paired transitions n * t period + t xjr2 consecutive transitions n * t period + t xjr1 msb t msu lsb t mhd t sckh t mdo ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl msb lsb
cyrf69213 document number: 001-07552 rev. *g page 79 of 85 figure 28. spi slave timing, cpha = 1 msb t ssu lsb t shd t sckh t sdo ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sss t ssh msb lsb
cyrf69213 document number: 001-07552 rev. *g page 80 of 85 figure 29. spi master timing, cpha = 0 figure 30. spi slave timing, cpha = 0 msb t msu lsb t mhd t sckh t mdo1 ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl t mdo lsb msb msb t ssu lsb t shd t sckh t sdo1 ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sdo lsb msb t sss t ssh
cyrf69213 document number: 001-07552 rev. *g page 81 of 85 ordering code definitions ordering information package ordering part number status 40-pin pb-free qfn 6 6 mm (sawn) CYRF69213-40LTXC in production 40-pin pb-free qfn 6 6 mm (punch) cyrf69213-40lfxc nrnd cy marketing code: rf = wireless (radio frequency) product line rf company id: cy = cypress part number 69213 40- pin package f = qfn; t = sawn qfn x = pb-free 40 l(f,t)x temperature range: commercial c
cyrf69213 document number: 001-07552 rev. *g page 82 of 85 package diagram figure 31. 40-pin qfn (6 6 1.0 mm) lt40b (3.5 3.5 mm) e-pad (sawn) package outline, 001-13190 001-13190 *h
cyrf69213 document number: 001-07552 rev. *g page 83 of 85 figure 32. 40-pin qfn (6 6 1.0 mm) lf40a/ly40a (3 .50 3.50 mm) e-pad (punch) package outline, 001-12917 [15] pad exposed solderable 001-12917 *c note 15. not recommended for new design.
cyrf69213 document number: 001-07552 rev. *g page 84 of 85 document history page document title: cyrf69213, programmable radio on chip low power document #: 001-07552 rev. ecn no. orig. of change submission date description of change ** 436355 oyr see ecn new advance data sheet. *a 501280 oyr see ecn preliminary data sheet. *b 631538 boo see ecn final datasheet. updated dc ch aracteristics table with characterization data. minor text changes removed all residual references to external crystal oscillator and gpio4 voltage regulator line/load regulation documented gpio capacitance and timing diagram included sleep and wake up sequence documented. ep1mode/ep2mode regi ster issue discussed updated radio function register descriptions changed l/d pin description changed rst capacitor from 0.1uf to 0.47uf *c 2447906 vny / vgt / aesa see ecn modified figure 1: vbat changed to vbat 0,1,2 for pins 36,6 and 9 drive level changed to 100uw figures 1and 3 have a 1 ohm resistor added between vreg and vcc radio register map summary has pfet disable added to bit 4 of pwr_ctrl_adr modified register map notes summary for the radio. modified p02cr to p03cr added a table to include properties of p01cr modified the encore ii register summary table to include properties of p01cr modified section on low power in sleep mode updated template *d 2661527 tge / pyrs 18/02/09 changed package spec to 001-12917 removed backward co mpatibility section changed "pfet disable" bit in register 0x0b to "rsvd". added text ?for rf activity, vcc=vbat=3.0 v-3.6 v? to radio function operating voltage *e 2899829 kku 03/26/2010 updated the following sections: pinouts , clock block diagram , clock architecture description , cpu clock during sleep mode , reset , sleep mode , and register summary *f 3550855 antg 03/15/2012 added new ordering part number for sawn type package added new package diagram for sawn type package. added a section ?receive spurious response? added note# 16 and provided reference to it in table 88 added ordering code definition updated the package diagram for punch type package *g 3717153 ankc 08/18/2012 updated ordering information (no change in part numbers, included a column ?status?). updated package diagram (spec 001-13190 (changed revision from *g to *h), added note 15 and referred the same note in figure 32 ). updated in new template.
document number: 001-07552 rev. *g revised august 18, 2012 page 85 of 85 wirelessusb, psoc, encore and proc are trademarks of cypress semiconductor corporation. all products and company names mentione d in this document may be the trademarks of their respective holders. cyrf69213 ? cypress semiconductor corporation, 2006-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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